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    Selectively locking memory locations within a microprocessor's on-chip cache
    1.
    发明授权
    Selectively locking memory locations within a microprocessor's on-chip cache 失效
    选择性地锁定微处理器内部缓存中的存储单元

    公开(公告)号：US5249286A

    公开(公告)日：1993-09-28

    申请号：US982031

    申请日：1992-11-24

    申请人： Donald B. Alpert ,  Oved Oz ,  Gideon Intrater ,  Reuven Marko ,  Alon Shacham

    发明人： Donald B. Alpert ,  Oved Oz ,  Gideon Intrater ,  Reuven Marko ,  Alon Shacham

    IPC分类号： G06F12/12

    CPC分类号： G06F12/126

    摘要： A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.

    摘要翻译： 一种微处理器架构，其包括将单个条目锁定到其集成指令高速缓存和数据高速缓存中的能力，同时使缓存的其余部分被解锁并可用于捕获微处理器的动态参考位置。 微处理器还包括锁定指令高速缓存条目的能力，而不需要在锁定过程期间执行指令。

    Parallel integrated circuit having DSP module and CPU core operable for switching between two independent asynchronous clock sources while the system continues executing instructions
    2.
    发明授权
    Parallel integrated circuit having DSP module and CPU core operable for switching between two independent asynchronous clock sources while the system continues executing instructions 失效
    具有DSP模块和CPU核的并行集成电路可操作用于在系统继续执行指令时在两个独立的异步时钟源之间切换

    公开(公告)号：US5603017A

    公开(公告)日：1997-02-11

    申请号：US309546

    申请日：1994-09-20

    申请人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

    发明人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F1/04

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

    摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

    Mechanism for handling non-maskable interrupt requests received from different sources
    3.
    发明授权
    Mechanism for handling non-maskable interrupt requests received from different sources 失效
    用于处理从不同来源接收的不可屏蔽中断请求的机制

    公开(公告)号：US5649208A

    公开(公告)日：1997-07-15

    申请号：US553012

    申请日：1995-11-03

    申请人： Gideon Intrater ,  Oved Oz ,  Meir Tsadik

    发明人： Gideon Intrater ,  Oved Oz ,  Meir Tsadik

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F9/46

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： The central processing unit of an integrated circuit data processing system includes both means for processing a first non-maskable interrupt (NMI) request received by the data processing system on a first NMI request line and means for processing a second NMI request received by the data processing system on a second NMI request line different from the first NMI request line and within a predefined time period after receipt of the first NMI request. Both. NMI requests are serviced by the data processing system even if the second NMI request is received prior to completion of processing of the first request.

    摘要翻译： 集成电路数据处理系统的中央处理单元包括用于处理由数据处理系统在第一NMI请求线上接收的第一不可屏蔽中断（NMI）请求的装置和用于处理由数据接收的第二NMI请求的装置的装置 处理系统在与第一NMI请求行不同的第二NMI请求行上并且在接收到第一NMI请求之后的预定时间段内。 都。 即使在完成第一个请求的处理之前接收到第二个NMI请求，NMI请求也由数据处理系统服务。

    Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of different frequencies while the CPU continues executing instructions
    4.
    发明授权
    Integrated circuit having CPU core operable for switching between two independent asynchronous clock sources of different frequencies while the CPU continues executing instructions 失效
    具有CPU核心的集成电路可操作用于在CPU继续执行指令时在不同频率的两个独立异步时钟源之间切换

    公开(公告)号：US5872960A

    公开(公告)日：1999-02-16

    申请号：US624879

    申请日：1996-03-27

    申请人： Oved Oz ,  Gideon Intrater ,  Yachin Afek

    发明人： Oved Oz ,  Gideon Intrater ,  Yachin Afek

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F1/04

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

    摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

    Integrated data processing system utilizing successive approximation analog to digital conversion and PWM for parallel disconnect
    6.
    发明授权
    Integrated data processing system utilizing successive approximation analog to digital conversion and PWM for parallel disconnect 失效
    采用逐次逼近模数转换和PWM并联断开的集成数据处理系统

    公开(公告)号：US5613149A

    公开(公告)日：1997-03-18

    申请号：US546187

    申请日：1995-10-20

    申请人： Yachin Afek ,  Oved Oz ,  Gideon Intrater

    发明人： Yachin Afek ,  Oved Oz ,  Gideon Intrater

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F11/00 ,  G06F15/16

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： An integrated circuit structure for use in identifying a value of an analog signal includes a central processing unit that executes instructions to perform data processing operations. The data processing operations include a successive approximation analog-to-dialog conversion operation to provide a digital value based upon an input data signal. A pulse with modulation (PWM) element converts the digital value to a square-wave output signal having a duty cycle corresponding to the digital value. A PWM element is adapted for connection to a low pass filter such that the square-wave output signal is provided as an input to the low pass filter. The low pass filter provides an output analog signal corresponding to the duty cycle of the square-wave output signal. An input port is adapted for connection to an output of a comparator. The comparator receives as inputs the output analog signal the low pass filter and the analog signal. The input port is connected to provide the output of the comparator as the input data signal to the central processing unit.

    摘要翻译： 用于识别模拟信号的值的集成电路结构包括执行指令以执行数据处理操作的中央处理单元。 数据处理操作包括逐次近似模拟对话转换操作，以基于输入数据信号提供数字值。 具有调制（PWM）元件的脉冲将数字值转换成具有对应于数字值的占空比的方波输出信号。 PWM元件适于连接到低通滤波器，使得方波输出信号被提供为低通滤波器的输入。 低通滤波器提供与方波输出信号的占空比对应的输出模拟信号。 输入端口适于连接到比较器的输出。 比较器接收低通滤波器和模拟信号的输出模拟信号作为输入。 连接输入端口，将比较器的输出作为输入数据信号提供给中央处理单元。

    Integrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnect
    7.
    发明授权
    Integrated data processing system having CPU core and parallel independently operating DSP module utilizing successive approximation analog to digital and PWM for parallel disconnect 失效
    具有CPU内核和并行独立运行的DSP模块的集成数据处理系统，利用逐次逼近模数和PWM并行断开

    公开(公告)号：US5491828A

    公开(公告)日：1996-02-13

    申请号：US307399

    申请日：1994-09-16

    申请人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

    发明人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F11/00 ,  G06F15/16

    CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

    摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

    摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

    Apparatus and method for discovering a scratch pad memory configuration
    10.
    发明申请
    Apparatus and method for discovering a scratch pad memory configuration 有权
    用于发现临时存储器存储器配置的装置和方法

    公开(公告)号：US20050102483A1

    公开(公告)日：2005-05-12

    申请号：US11003120

    申请日：2004-12-03

    申请人： Ryan Kinter ,  Scott McCoy ,  Gideon Intrater

    发明人： Ryan Kinter ,  Scott McCoy ,  Gideon Intrater

    IPC分类号： G06F12/06 ,  G06F12/00

    CPC分类号： G06F12/0684

    摘要： The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configuration of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the configuration file. The invention also includes an embedded processor with a processor core and scratch pad memory connected to the processor core. The scratch pad memory includes a set of scratch pad regions. The scratch pad memory stores values characterizing base addresses and region size values of the set of scratch pad regions.

    摘要翻译： 本发明包括一种调试嵌入式处理器的方法。 访问嵌入式处理器的便携式存储器以形成表征便笺式存储器的暂存区域区域的配置的配置文件。 嵌入式处理器使用配置文件中的信息进行调试。 本发明还包括具有连接到处理器核心的处理器核心和临时存储器存储器的嵌入式处理器。 便笺本式存储器包括一组暂存区域。 临时存储器存储表征该组暂存区区域的基址和区域大小值的值。