公开(公告)号：US06361402B1

公开(公告)日：2002-03-26

申请号：US09427492

申请日：1999-10-26

申请人： Donald F. Canaperi ,  Rangarajan Jagannathan ,  Mahadevaiyer Krishnan ,  Max G. Levy ,  Uma Satyendra ,  Matthew Sendelbach ,  James A. Tornello ,  William Wille

发明人： Donald F. Canaperi ,  Rangarajan Jagannathan ,  Mahadevaiyer Krishnan ,  Max G. Levy ,  Uma Satyendra ,  Matthew Sendelbach ,  James A. Tornello ,  William Wille

IPC分类号： B24B100

CPC分类号： B24B37/0056 ,  B24B37/044 ,  H01L21/31053 ,  H01L21/76819

摘要： A method for polishing an object having a layer of photoresist, the method, employing the following steps: a) applying a layer of slurry on an a layer of photoresist on an object having a first and a second side, the layer of photoresist on one of the first and second side, the object having a center axis perpendicular to the first and second side; b) contacting the layer of slurry with a pad having a first and second side, the first side of the pad exerting a force on the slurry.

摘要翻译： 一种用于抛光具有光致抗蚀剂层的物体的方法，该方法采用以下步骤：a）在具有第一和第二侧的物体上的一层光致抗蚀剂上施加一层浆料，一层光致抗蚀剂 所述第一和第二侧的物体具有垂直于第一和第二侧的中心轴; b）使浆料层与具有第一和第二侧的垫接触，垫的第一侧在浆料上施加力 。

公开(公告)号：US20070122965A1

公开(公告)日：2007-05-31

申请号：US11668790

申请日：2007-01-30

申请人： Dureseti Chidambarrao ,  William Henson ,  Kern Rim ,  William Wille

发明人： Dureseti Chidambarrao ,  William Henson ,  Kern Rim ,  William Wille

IPC分类号： H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/7842

摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.

公开(公告)号：US20070069294A1

公开(公告)日：2007-03-29

申请号：US11162953

申请日：2005-09-29

申请人： Dureseti Chidambarrao ,  William Henson ,  Kern Rim ,  William Wille

发明人： Dureseti Chidambarrao ,  William Henson ,  Kern Rim ,  William Wille

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/7842

摘要： A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensile nitride films in the shallow trench isolation (STI) process is described. High values of stress are achieved when the method is applied to a selective SOI architecture.

摘要翻译： 描述了一种使用高应力氮化物膜与选择性绝缘体上半导体（SOI）器件结构结合的在不同导电性的MOS晶体管的沟道中应力的方法。 描述了在浅沟槽隔离（STI）工艺中使用压缩和拉伸氮化物膜的方法。 当将该方法应用于选择性SOI结构时，实现高应力值。

公开(公告)号：US20050023581A1

公开(公告)日：2005-02-03

申请号：US10604533

申请日：2003-07-29

申请人： Joachim Nuetzel ,  Xian Jay Ning ,  William Wille

发明人： Joachim Nuetzel ,  Xian Jay Ning ,  William Wille

IPC分类号： G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  H01L21/00 ,  H01L29/76 ,  H01L31/062 ,  H01L43/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15

摘要： A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.

摘要翻译： 一种用于在磁随机存取存储器（MRAM）装置中形成互连结构的装置结构和方法。 在示例性实施例中，该方法包括在下部金属化层面上限定磁性层叠层，磁性堆叠层包括设置在一对铁磁层之间的非铁磁层。 导电硬掩模被定义在磁性堆叠层上，然后去除硬掩模和磁性堆叠层的选定部分，由此形成磁性隧道结（MTJ）堆叠的阵列。 MTJ堆叠包括磁堆叠层和硬掩模的剩余部分，其中硬掩模在磁堆叠层和随后形成在MTJ叠层之上的上金属化层之间形成自对准接触。