Abstract:
A wireless communication device is disclosed wherein isolation buffers couple to respective active circuits or stages of the device to convey test information regarding such active circuits to a test data line from which status information may be collected. The communication device operates in two modes, namely a normal operational mode wherein the isolation buffers effectively short spurious emissions from the active circuits to a ground, and a test mode wherein the isolation buffers may convey test information from a selected active circuit to the test data line. The isolation buffers prevent spurious emissions from escaping the active circuits to which they are coupled and prevent spurious emissions from traveling from active circuit to active circuit over the test data line throughout the wireless device.
Abstract:
The digital interface between the baseband section and the RF transceiver section of a wireless communication device may cause undesired pulling to an impedance sensitive portion of the RF transceiver section. In one embodiment, an original interface signal that exhibits a duty cycle is modified by an interface control block in the baseband section. The resultant modified interface signal exhibits a duty cycle less than the duty cycle of the original interface signal. In this manner, when the modified interface signal is applied to the RF transceiver section, less pulling of the impedance sensitive portion occurs than if the original interface signal were applied directly to the RF transceiver section.
Abstract:
A voltage regulator configured to receive a supply voltage from a voltage supply and provide a regulated voltage to digital circuitry is provided. The voltage regulator comprises first circuitry configured to inhibit high frequency energy generated by the digital circuitry from transmitting into the voltage supply, second circuitry configured to inhibit low frequency energy generated by the digital circuitry from transmitting into the voltage supply, and third circuitry configured to maintain the regulated voltage at a substantially constant value in response to a current drawn by the digital circuitry.
Abstract:
Interchangeable high band low-noise-amplifiers (LNAs) and low band low-noise-amplifiers (LNAs) and related methods are disclosed that greatly enhance the efficiency of designing handsets for different combinations of frequency bands. The input signals to particular pins on a receiver or transceiver integrated circuit (IC) are swappable such that multiple frequency bands can be input to the same input pins thereby allowing for simplified system design. Efficient programmable techniques are also disclosed for controlling a swap mode within communication ICs. These interchangeable or band swappable input paths, for example, can be utilized to allow interchangeability between high band (PCS, DCS) and low band (GSM, E-GSM) inputs for cellular communications. In this way, for example, handset manufacturers can build a single printed circuit board (PCB) that can be utilized for cellular communications in the United States of America, where 850 MHz (GSM) and 1900 MHz (PCS) bands are utilized, and in Europe, wherein 900 MHz (E-GSM) and 1800 MHz (DCS) bands are utilized.
Abstract:
A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired (1302) for use in a receiver system (15) using a first known signal associated with a first signal band during a startup mode. The first image correction factor is adjusted incrementally (1310) during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received (1324) using the first image correction factor during the normal operation mode.
Abstract:
Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.
Abstract:
In one embodiment, the present invention includes a capacitor array that may provide a selected capacitance to a digitally controlled crystal oscillator (DCXO). The array may include multiple sections each having at least one array portion, where each section is to receive different significant portions of a digital control value. The different sections may have different coding schemes. Other embodiments are described and claimed.
Abstract:
Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.
Abstract:
A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined. When the receiver switches to a normal operating mode, the frequency synthesizer, ADCs and DSP are clocked by a main clock signal instead of the divided down test tone, and the test tone is removed from the mixers.
Abstract:
In one embodiment, the present invention includes a frequency divider that has an I channel to provide an I channel phase; and a Q channel to provide a Q channel phase, in which the I and the Q channels are mirrored with respect to an axis therebetween. The axis may also be substantially coincident with a center axis of a device incorporating the frequency divider, such as a transceiver.