公开(公告)号：US20130043958A1

公开(公告)日：2013-02-21

申请号：US13210280

申请日：2011-08-15

申请人： Yen-Horng Chen ,  Wen-Chang Lee ,  Augusto Marques ,  Xiaochuan Guo

发明人： Yen-Horng Chen ,  Wen-Chang Lee ,  Augusto Marques ,  Xiaochuan Guo

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1265 ,  H03J2200/10

摘要： A digitally controlled oscillator is provided. The digitally controlled oscillator includes a pair of transistors cross-coupled to each other, a switched capacitor array coupled to the pair of transistors and a plurality of frequency tracking units coupled to the pair of transistors. The pair of transistors provides an output signal. The switched capacitor array tunes a frequency of the output signal. The frequency tracking units tune the frequency of the output signal to a target frequency. At least one of the frequency tracking units is capable of selectively providing a first capacitance and a second capacitance. A tuning resolution of the frequency tracking unit is determined by a difference between the first and second capacitances.

摘要翻译： 提供数字控制振荡器。 数字控制振荡器包括彼此交叉耦合的一对晶体管，耦合到该对晶体管的开关电容器阵列和耦合到该对晶体管的多个频率跟踪单元。 一对晶体管提供输出信号。 开关电容阵列调节输出信号的频率。 频率跟踪单元将输出信号的频率调谐到目标频率。 频率跟踪单元中的至少一个能够选择性地提供第一电容和第二电容。 频率跟踪单元的调谐分辨率由第一和第二电容之间的差确定。

公开(公告)号：US20120074998A1

公开(公告)日：2012-03-29

申请号：US13115126

申请日：2011-05-25

申请人： Stephen Jonathan Brett ,  Augusto Marques ,  Jonathan Richard STRANGE

发明人： Stephen Jonathan Brett ,  Augusto Marques ,  Jonathan Richard STRANGE

IPC分类号： H03L7/08

CPC分类号： H03L7/099 ,  H03L1/022 ,  H03L2207/06

摘要： An integrated circuit device for compensating frequency drift of a controllable oscillator is described. The integrated circuit device includes at least one compensation module including: an input for receiving at least an indication of a frequency control signal (vci) from at least one frequency control module; and an output for providing at least one compensation signal (vct) to the controllable oscillator. The at least one compensation module is arranged to compare the at least indication of the frequency control signal (vci) with a reference voltage signal (vref); and generate the at least one compensation signal (vct) based at least partly on the comparison of the indication of the frequency control signal (vci) to the reference voltage signal (vref).

摘要翻译： 描述了用于补偿可控振荡器的频率漂移的集成电路装置。 集成电路装置包括至少一个补偿模块，包括：用于从至少一个频率控制模块接收至少一个频率控制信号（vci）的指示的输入; 以及用于向可控振荡器提供至少一个补偿信号（vct）的输出。 所述至少一个补偿模块被布置为将所述频率控制信号（vci）的所述至少指示与参考电压信号（vref）进行比较; 并且至少部分地基于频率控制信号（vci）的指示与参考电压信号（vref）的比较来生成至少一个补偿信号（vct）。

公开(公告)号：US20070057743A1

公开(公告)日：2007-03-15

申请号：US11227421

申请日：2005-09-14

申请人： Peter Vancorenland ,  Lysander Lim ,  Augusto Marques ,  Scott Willingham

发明人： Peter Vancorenland ,  Lysander Lim ,  Augusto Marques ,  Scott Willingham

IPC分类号： H03B5/12

CPC分类号： H03J3/185 ,  H03B5/1243 ,  H03B5/1293 ,  H03B2200/0062 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03J7/10 ,  H03J2200/36 ,  H03L7/099

摘要： An oscillator includes a plurality of varactor cells to receive a control signal to control a frequency of the oscillator. Each of the varactor cells includes a switch that includes a first terninal to receive the control signal and a second terminal such that the switch operates to control a capacitance of the varactor cell in response to a voltage between the first and second terminals. The oscillator includes a bias circuit to provide a different bias voltage to each second terminal and an amplifier that is coupled to the varactor cells to generate an oscillating signal.

摘要翻译： 振荡器包括多个变容二极管单元，用于接收控制信号以控制振荡器的频率。 每个变容二极管单元包括开关，该开关包括用于接收控制信号的第一三极管和第二端子，使得开关操作以响应于第一和第二端子之间的电压来控制变容二极管单元的电容。 振荡器包括偏置电路，以向每个第二端子提供不同的偏置电压，以及耦合到变容二极管单元以产生振荡信号的放大器。

公开(公告)号：US20070057739A1

公开(公告)日：2007-03-15

申请号：US11226041

申请日：2005-09-14

申请人： James Maligeorgos ,  Donald Kerth ,  Augusto Marques

发明人： James Maligeorgos ,  Donald Kerth ,  Augusto Marques

IPC分类号： H03B5/12

CPC分类号： H03B5/366 ,  H03B2200/005 ,  H03B2201/0208 ,  H03B2201/0266

摘要： In one embodiment, the present invention includes a capacitor array that may provide a selected capacitance to a digitally controlled crystal oscillator (DCXO). The array may include multiple sections each having at least one array portion, where each section is to receive different significant portions of a digital control value. The different sections may have different coding schemes. Other embodiments are described and claimed.

公开(公告)号：US20070054629A1

公开(公告)日：2007-03-08

申请号：US10730404

申请日：2003-12-08

申请人： James Maligeorgos ,  Augusto Marques ,  Lysander Lim ,  G. Tuttle ,  Aslamali Rafi ,  Tod Paulus ,  Gregory Uehara ,  Jeffrey Scott ,  Richard Behrens ,  Donald Kerth ,  G. Vishakhadatta ,  Vishnu Srinivasan ,  Caiyi Wang

发明人： James Maligeorgos ,  Augusto Marques ,  Lysander Lim ,  G. Tuttle ,  Aslamali Rafi ,  Tod Paulus ,  Gregory Uehara ,  Jeffrey Scott ,  Richard Behrens ,  Donald Kerth ,  G. Vishakhadatta ,  Vishnu Srinivasan ,  Caiyi Wang

IPC分类号： H04B1/38

CPC分类号： H04B1/30 ,  H03J2200/10 ,  H04L27/0002

摘要： Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry. Automatic frequency control (AFC) circuitry may be integrated with other components of RF circuitry and may generate frequency control signals for the frequency modification circuitry based on, for example, a signal received from a temperature sensor. Digital-to-analog converter (DAC) circuitry may be integrated with other components of RF circuitry to enable all-digital frequency control communications from baseband processor circuitry to RF circuitry.

摘要翻译： 包括生成具有可变频率的参考信号的晶体振荡器电路的收发器电路和频率修改电路的射频（RF）设备的组件可以以各种方式被划分，例如作为一个或多个单独的集成电路。 频率修改电路可以被实现为包括数字控制的晶体振荡器（“DCXO”）电路和晶体的晶体振荡器电路的一部分。 频率修改电路可以包括至少一个可变电容器件，并且可以用于产生具有可调频率的参考信号。 可调参考信号可以被提供给RF装置的其他部件，和/或RF装置可以被配置为向基带处理器电路提供可调参考信号。 自动频率控制（AFC）电路可以与RF电路的其它组件集成，并且可以基于例如从温度传感器接收的信号来生成用于频率修改电路的频率控制信号。 数模转换器（DAC）电路可以与RF电路的其他部件集成，以实现从基带处理器电路到RF电路的全数字频率控制通信。

公开(公告)号：US20050212585A1

公开(公告)日：2005-09-29

申请号：US10810039

申请日：2004-03-26

申请人： Donald Kerth ,  Augusto Marques ,  Dylan Hester ,  Russell Croman

发明人： Donald Kerth ,  Augusto Marques ,  Dylan Hester ,  Russell Croman

IPC分类号： H02J1/00 ,  H03B5/04 ,  H03F1/30 ,  H03K3/01

CPC分类号： H03F1/301 ,  H03B5/04

摘要： A bias system is disclosed including a calibration bus to which a controller, a reference bias source, a master bias source, and first and second slave bias sources are coupled. The controller varies a control code sent over the calibration bus to the master bias source until a particular control code is found that causes the bias signal of the master bias source to equal a desired bias value which is provided by the reference bias source. The controller then sends the particular control code to the first and second slave bias sources to cause the first and second slave bias sources to generate a bias signal having the same desired bias value as the master bias source. Isolation between load circuits coupled to the first and second bias sources is thus enhanced while providing low noise, stable operation

摘要翻译： 公开了一种偏置系统，其包括校准总线，控制器，参考偏置源，主偏置源以及第一和第二从属偏置源耦合到校准总线。 控制器将通过校准总线发送的控制代码改变为主偏置源，直到找到导致主偏置源的偏置信号等于由参考偏置源提供的期望偏置值的特定控制代码。 然后，控制器将特定控制码发送到第一和第二从属偏置源，以使第一和第二从属偏置源产生具有与主偏置源相同的期望偏置值的偏置信号。 因此，耦合到第一和第二偏置源的负载电路之间的隔离增强，同时提供低噪声，稳定的操作

公开(公告)号：US08570107B2

公开(公告)日：2013-10-29

申请号：US13299347

申请日：2011-11-17

申请人： Xiaochuan Guo ,  Wen-Chang Lee ,  Chii-Horng Chen ,  Augusto Marques

发明人： Xiaochuan Guo ,  Wen-Chang Lee ,  Chii-Horng Chen ,  Augusto Marques

IPC分类号： H03L7/087 ,  H03L7/085

CPC分类号： H03L7/103 ,  H03L7/099 ,  H03L7/1976 ,  H03L2207/06 ,  H03L2207/50

摘要： A clock generating apparatus includes: a time-to-digital converter (TDC) arranged to convert a timing difference between a reference clock and a variable clock to generate a digital value; a calibrating device arranged to generate a control signal according to the digital value and the reference clock; a controllable oscillator arranged to generate an oscillating signal according to the control signal and the digital value; and a feedback device arranged to generate the variable clock to the TDC according to the oscillating signal, and the calibrating device calibrates the controllable oscillator to make the oscillating signal have a target oscillating frequency.

摘要翻译： 时钟发生装置包括：时间数字转换器（TDC），被配置为转换参考时钟和可变时钟之间的定时差以产生数字值; 校准装置，被配置为根据数字值和参考时钟产生控制信号; 可控振荡器，被配置为根据控制信号和数字值产生振荡信号; 以及反馈装置，其被配置为根据振荡信号向TDC生成可变时钟，并且校准装置校准可控振荡器以使振荡信号具有目标振荡频率。

公开(公告)号：US20130142274A1

公开(公告)日：2013-06-06

申请号：US13610912

申请日：2012-09-12

申请人： Hsiang-Hui Chang ,  Augusto Marques ,  Li-Shin Lai ,  Chih-Hao Sun ,  George Chien

发明人： Hsiang-Hui Chang ,  Augusto Marques ,  Li-Shin Lai ,  Chih-Hao Sun ,  George Chien

IPC分类号： H04L25/02

CPC分类号： H04L25/02 ,  H04L27/0002

摘要： An embodiment of the invention provides a sliced transmitter front-end (TX FE). The sliced TX FE includes first TX FE slices and a second TX FE slice that are connected in parallel. As a whole the first TX FE slices contributes a high-gain section to a superimposed gain range of the sliced TX FE. The second TX FE slice has a gain range that constitutes a low-gain section of the superimposed gain range of the sliced TX FE. A minimum gain of the gain range of the second TX FE slice is smaller than a minimum gain of the high-gain section.

摘要翻译： 本发明的实施例提供了一个切片发射机前端（TX FE）。 分片TX FE包括并行连接的第一TX FE片和第二TX FE片。 作为整体，第一TX FE片对切片TX FE的叠加增益范围贡献高增益部分。 第二TX FE切片具有构成切片TX FE的叠加增益范围的低增益部分的增益范围。 第二TX FE片的增益范围的最小增益小于高增益部分的最小增益。

公开(公告)号：US20070060069A1

公开(公告)日：2007-03-15

申请号：US11341149

申请日：2006-01-27

申请人： Donald Kerth ,  James Maligeorgos ,  Xiaochuan Guo ,  Augusto Marques

发明人： Donald Kerth ,  James Maligeorgos ,  Xiaochuan Guo ,  Augusto Marques

IPC分类号： H04B17/00

CPC分类号： H04B17/0085

摘要： A wireless communication device is disclosed wherein isolation buffers couple to respective active circuits or stages of the device to convey test information regarding such active circuits to a test data line from which status information may be collected. The communication device operates in two modes, namely a normal operational mode wherein the isolation buffers effectively short spurious emissions from the active circuits to a ground, and a test mode wherein the isolation buffers may convey test information from a selected active circuit to the test data line. The isolation buffers prevent spurious emissions from escaping the active circuits to which they are coupled and prevent spurious emissions from traveling from active circuit to active circuit over the test data line throughout the wireless device.

摘要翻译： 公开了一种无线通信设备，其中隔离缓冲器耦合到设备的相应有效电路或级，以将关于这种有源电路的测试信息传送到可以从其收集状态信息的测试数据线。 通信设备以两种模式操作，即正常操作模式，其中隔离缓冲器有效地将有源电路的杂散发射短路到地，以及测试模式，其中隔离缓冲器可以将测试信息从所选择的有源电路传送到测试数据 线。 隔离缓冲器防止杂散发射从它们耦合到的有源电路中逸出，并防止杂散发射通过整个无线设备的测试数据线从有源电路传播到有源电路。

公开(公告)号：US20050253223A1

公开(公告)日：2005-11-17

申请号：US11014143

申请日：2004-12-16

申请人： Augusto Marques

发明人： Augusto Marques

IPC分类号： H01L23/522 ,  H01L23/60 ,  C22C29/00 ,  H01L23/552

CPC分类号： H01L23/5223 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal mesh structure for use in an integrated circuit is described. In one embodiment, a semiconductor integrated circuit includes a first region including, for example, a device layer having one or more active semiconductor devices. The circuit also includes a second region, which may include a metalization layer including circuit wires. The circuit further includes a layer of metal mesh interposed between the first and second regions, and which may be implemented on at least a portion of another metalization layer.

摘要翻译： 描述了用于集成电路的金属网格结构。 在一个实施例中，半导体集成电路包括包括例如具有一个或多个有源半导体器件的器件层的第一区域。 电路还包括第二区域，其可以包括包括电路线的金属化层。 电路还包括介于第一和第二区域之间的金属网的层，并且其可以在另一金属化层的至少一部分上实现。