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    METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT
    1.
    发明申请
    METHOD AND APPARATUS FOR PERFORMING LOGIC BUILT-IN SELF-TESTING OF AN INTEGRATED CIRCUIT 有权
    用于执行集成电路逻辑内置自检的方法和装置

    公开(公告)号：US20090307548A1

    公开(公告)日：2009-12-10

    申请号：US12133830

    申请日：2008-06-05

    申请人： Donato O. Forlenza ,  Orazio P. Forlenza ,  Bryan J. Robbins ,  Phong T. Tran

    发明人： Donato O. Forlenza ,  Orazio P. Forlenza ,  Bryan J. Robbins ,  Phong T. Tran

    IPC分类号： G01R31/3187 ,  G06F11/00

    CPC分类号： G01R31/318533

    摘要： A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.

    摘要翻译： 公开了一种用于执行集成电路的逻辑内置自检的方法。 该方法包括执行刷新和扫描测试以确定扫描链是否正常工作。 如果其中一个扫描链无法正常工作，则逻辑内置自检终止。 如果每个扫描链都正常工作，则执行支持LBIST的测试用设计逻辑的结构测试，以确定LBIST设计测试逻辑是否正确运行。 如果LBIST设计测试逻辑不能正常工作，则逻辑内置自检终止。 如果LBIST设计测试逻辑正常工作，则使用支持LBIST设计测试的逻辑执行功能组合逻辑的电平敏感扫描设计测试，以确定集成电路是否正常工作。

    Method and apparatus for performing logic built-in self-testing of an integrated circuit
    2.
    发明授权
    Method and apparatus for performing logic built-in self-testing of an integrated circuit 有权
    用于执行集成电路内置自检的逻辑的方法和装置

    公开(公告)号：US07934134B2

    公开(公告)日：2011-04-26

    申请号：US12133830

    申请日：2008-06-05

    申请人： Donato O. Forlenza ,  Orazio P. Forlenza ,  Bryan J. Robbins ,  Phong T. Tran

    发明人： Donato O. Forlenza ,  Orazio P. Forlenza ,  Bryan J. Robbins ,  Phong T. Tran

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318533

    摘要： A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.

    摘要翻译： 公开了一种用于执行集成电路的逻辑内置自检的方法。 该方法包括执行刷新和扫描测试以确定扫描链是否正常工作。 如果其中一个扫描链无法正常工作，则逻辑内置自检终止。 如果每个扫描链都正常工作，则执行支持LBIST的测试用设计逻辑的结构测试，以确定LBIST设计测试逻辑是否正确运行。 如果LBIST设计测试逻辑不能正常工作，则逻辑内置自检终止。 如果LBIST设计测试逻辑正常工作，则使用支持LBIST设计测试的逻辑执行功能组合逻辑的电平敏感扫描设计测试，以确定集成电路是否正常工作。

    Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG
    5.
    发明申请
    Automated System and Processing for Expedient Diagnosis of Broken Shift Registers Latch Chains Using JTAG 有权
    自动系统和处理，以便使用JTAG来切换移位寄存器锁存链

    公开(公告)号：US20090210763A1

    公开(公告)日：2009-08-20

    申请号：US12032655

    申请日：2008-02-16

    申请人： Joseph Eckelman ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  Robert B. Gass ,  Phong T. Tran

    发明人： Joseph Eckelman ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  Robert B. Gass ,  Phong T. Tran

    IPC分类号： G01R31/3187 ,  G06F11/00

    CPC分类号： G01R31/318544 ,  G01R31/318536

    摘要： This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

    摘要翻译： 本发明涉及使用JTAG功能测试模式和执行者来解决在所有锁存系统端口中以串行或侧向宽边插入方式诊断断层扫描链的问题，并且有效地分析响应数据以便容易地识别 切换和非切换锁存器与下一个最后一个非切换锁存器是故障扫描链中的断点。 这种综合的锁定扰动结合迭代诊断算法用于识别并确定在这种断开的扫描链中的有缺陷的位置。 这种JTAG功能测试功能和最终从其导出的JTAG测试模式可以承载不同的形式和起源，一些产品外部和产品内部。

    Automated system and processing for expedient diagnosis of broken shift registers latch chains
    6.
    发明授权
    Automated system and processing for expedient diagnosis of broken shift registers latch chains 有权
    自动化系统和处理方便诊断破碎的移位寄存器锁链

    公开(公告)号：US07908532B2

    公开(公告)日：2011-03-15

    申请号：US12032655

    申请日：2008-02-16

    申请人： Joseph Eckelman ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  Robert B. Gass ,  Phong T. Tran

    发明人： Joseph Eckelman ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  Robert B. Gass ,  Phong T. Tran

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318544 ,  G01R31/318536

    摘要： This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.

    摘要翻译： 本发明涉及使用JTAG功能测试模式和执行者来解决在所有锁存系统端口中以串行或侧向宽边插入方式诊断断层扫描链的问题，并且有效地分析响应数据以便容易地识别 切换和非切换锁存器与下一个最后一个非切换锁存器是故障扫描链中的断点。 这种综合的锁定扰动结合迭代诊断算法用于识别并确定在这种断开的扫描链中的有缺陷的位置。 这种JTAG功能测试功能和最终从其导出的JTAG测试模式可以承载不同的形式和起源，一些产品外部和产品内部。

    AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns
    8.
    发明申请
    AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns 审中-公开
    AC扫描诊断方法和利用功能体系结构验证模式的设备

    公开(公告)号：US20090210761A1

    公开(公告)日：2009-08-20

    申请号：US12031930

    申请日：2008-02-15

    申请人： Donato O. Forlenza ,  Orazio P. Forlenza ,  Phong T. Tran

    发明人： Donato O. Forlenza ,  Orazio P. Forlenza ,  Phong T. Tran

    IPC分类号： G06F11/25 ,  G06F11/27 ,  G06F11/263

    CPC分类号： G06F11/267 ,  G01R31/318544

    摘要： A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional Architecture Verification Patterns (AVPs) for enabling rapidly localizing identified defects to a failing Shift Register Latch (SRL). An Architecture Verification Pattern (AVP) test pattern set is generated using a chip design input and simulation. AVP test vectors are applied for starting chip clocks and initiating testing, such as Logic Built-In-Self-Test (LBIST).

    摘要翻译： 提供了一种方法，装置和计算机程序产品，用于实现使用功能架构验证模式（AVP）的待测集成电路芯片中的延迟和AC扫描链缺陷的AC扫描诊断，以使快速定位故障移位寄存器锁存器 SRL）。 使用芯片设计输入和仿真生成架构验证模式（AVP）测试模式集。 应用AVP测试矢量启动芯片时钟并启动测试，如逻辑内置自检（LBIST）。

    Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain
    9.
    发明授权
    Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain 失效
    用于使用耦合到扫描链的保险丝诊断扫描链故障的方法，装置和计算机程序产品

    公开(公告)号：US07392449B2

    公开(公告)日：2008-06-24

    申请号：US11956480

    申请日：2007-12-14

    申请人： Todd M. Burdine ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  William J. Hurley ,  Phong T. Tran

    发明人： Todd M. Burdine ,  Donato O. Forlenza ,  Orazio P. Forlenza ,  William J. Hurley ,  Phong T. Tran

    IPC分类号： G01R31/28

    CPC分类号： G06F11/2215

    摘要： A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.

    摘要翻译： 提供了实现扫描链诊断技术的方法，装置和计算机程序产品。 诊断技术包括使用耦合到扫描链的锁存器的熔丝将已知逻辑值加载到扫描链的已知位置处的锁存器中，然后从扫描链中卸载值，并且如果扫描链有缺陷（例如， 基于卸载的逻辑值），然后通过与已加载逻辑值的扫描链中的缺陷通过经由保险丝加载了已知逻辑值的扫描链的锁存器的已知位置进行比较来定位扫描链中的缺陷。 可以使用每n个锁存器在链上周期性间隔的保险丝对扫描链进行预先设计，以便于扫描链中检测到的缺陷的随后定位。