公开(公告)号：US06444505B1

公开(公告)日：2002-09-03

申请号：US09678552

申请日：2000-10-04

申请人： Dou-I Chen ,  Jr-Hong Chen ,  Pi-Fu Chen ,  Wung-Ui Huang

发明人： Dou-I Chen ,  Jr-Hong Chen ,  Pi-Fu Chen ,  Wung-Ui Huang

IPC分类号： H01L2100

CPC分类号： H01L29/66765 ,  H01L29/78636

摘要： Within a method for forming a thin film transistor (TFT) structure, there is first provided a substrate. There is then formed over the substrate a gate electrode. There is then formed adjacent to the gate electrode but not covering a top surface of the gate electrode a backfilling dielectric layer. There is then formed over and covering the top surface of the gate electrode a gate dielectric layer. There is then formed over and covering the gate dielectric layer an active semiconductor layer. Finally, there is then formed over and in electrical communication with the active semiconductor layer a pair of source/drain electrodes, where the pair of source/drain electrodes having a separation distance which defines a channel region of the active semiconductor layer. The method for forming the thin film transistor (TFT) structure contemplates a thin film transistor (TFT) structure fabricated in accord with the method for forming the thin film transistor (TFT) structure. The method provides the thin film transistor (TFT) structure with enhanced functionality and reliability.

摘要翻译： 在用于形成薄膜晶体管（TFT）结构的方法中，首先提供基板。 然后在衬底上形成栅电极。 然后形成在栅电极附近，但不覆盖栅电极的顶表面的回填电介质层。 然后在栅电极的顶表面上形成栅极电介质层。 然后形成并覆盖栅极电介质层有源半导体层。 最后，然后在有源半导体层上形成一对源/漏电极，其中一对源极/漏极具有限定有源半导体层的沟道区的间隔距离。 用于形成薄膜晶体管（TFT）结构的方法考虑了根据用于形成薄膜晶体管（TFT）结构的方法制造的薄膜晶体管（TFT）结构。 该方法提供了具有增强的功能和可靠性的薄膜晶体管（TFT）结构。

公开(公告)号：US06479398B1

公开(公告)日：2002-11-12

申请号：US09692247

申请日：2000-10-18

申请人： Jr-Hong Chen ,  Jeng-Hung Sun ,  Hsixg-Ju Sung ,  Pi-Fu Chen ,  Dou-I Chen

发明人： Jr-Hong Chen ,  Jeng-Hung Sun ,  Hsixg-Ju Sung ,  Pi-Fu Chen ,  Dou-I Chen

IPC分类号： H01L21302

CPC分类号： H01L29/66765 ,  H01L29/78669

摘要： A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n+ amorphous-silicon layer and a metal layer. The metal layer defines a source electrode and a drain electrode. The structure simplifies the photolithography process by using a less number of masks to manufacture thin film transistors. It also reduces the occurrence of open circuits in the first metal (MI) layer or short circuits between the MI layer and the second metal (MII) layer caused by the photoresist residue or particle contamination. The manufacturing method combines a conventional back-channel-etched (BCE) reduced mask process and a two-step exposure technology. The two-step exposure technology uses two photoresist pattern masks. One is a pattern mask for complete exposure with higher light intensity and the other is a pattern mask for incomplete exposure with lower light intensity. The photoresist pattern with incomplete exposure is then etched by an O2 plasma etching process. The amorphous-silicon layer and the metal layer has the characteristic of an island metal masking structure that protects the active layer from plasma damage in plasma etching process.

摘要翻译： 非晶硅薄膜晶体管阵列的结构包括基板，栅电极，栅绝缘层，非晶硅有源层，n +非晶硅层和金属层。 金属层限定了源电极和漏电极。 该结构通过使用较少数量的掩模来制造薄膜晶体管来简化光刻工艺。 它还减少了第一金属（MI）层中的开路的发生或由光致抗蚀剂残留物或颗粒污染引起的MI层和第二金属（MII）层之间的短路。 该制造方法结合了常规的背沟道蚀刻（BCE）减少掩模工艺和两步曝光技术。 两步曝光技术使用两个光刻胶图案掩模。 一种是具有较高光强度的完全曝光的图案掩模，另一种是具有较低光强度的不完全曝光的图案掩模。 然后通过O 2等离子体蚀刻工艺蚀刻具有不完全曝光的光致抗蚀剂图案。 非晶硅层和金属层具有在等离子体蚀刻工艺中保护有源层免受等离子体损伤的岛金属掩蔽结构的特征。

公开(公告)号：US06534350B2

公开(公告)日：2003-03-18

申请号：US09920877

申请日：2001-08-02

申请人： Chih-Chiang Chen ,  Kun-Chih Lin ,  Chung-Shu Chang ,  Wen-Yu Huang ,  Pi-Fu Chen

发明人： Chih-Chiang Chen ,  Kun-Chih Lin ,  Chung-Shu Chang ,  Wen-Yu Huang ,  Pi-Fu Chen

IPC分类号： H01L2100

CPC分类号： H01L29/66757 ,  H01L29/4908 ,  H01L29/78609 ,  H01L29/78621 ,  H01L29/78675

摘要： A method for fabricating a low temperature polysilicon thin film transistor incorporating a channel passivation step is described. The method achieves dopant ion activation in a polysilicon gate by using laser irradiation, however, with an additional insulating material layer such as SiOx or SixNy overlying and protecting the channel portion of the polysilicon gate. Any possible contamination by residual photoresist material after a photoresist removal step on the channel portion of the polysilicon gate can thus be avoided. Furthermore, deficiencies such as dopant ions out-diffusion and lateral diffusion can be avoided. The leakage current of the thin film transistors formed by the present invention method is significantly reduced when compared to those formed by a conventional method.

摘要翻译： 描述了一种制造并入通道钝化步骤的低温多晶硅薄膜晶体管的制造方法。 该方法通过使用激光照射在多晶硅栅极中实现掺杂剂离子活化，然而，通过覆盖并保护多晶硅栅极的沟道部分的诸如SiOx或SixNy的附加绝缘材料层来实现掺杂剂离子激活。 因此，可以避免在多晶硅栅极的沟道部分上的光致抗蚀剂去除步骤之后残留的光致抗蚀剂材料的任何可能的污染。 此外，可以避免诸如掺杂剂离子扩散和横向扩散的缺陷。 与通过常规方法形成的薄膜晶体管相比，通过本发明方法形成的薄膜晶体管的漏电流显着降低。

公开(公告)号：US06670224B2

公开(公告)日：2003-12-30

申请号：US10033934

申请日：2002-01-03

申请人： Chi-shen Lee ,  Ting-Kuo Chang ,  Pi-Fu Chen ,  Yu-Ming Kang ,  Yuan-Tung Dai

发明人： Chi-shen Lee ,  Ting-Kuo Chang ,  Pi-Fu Chen ,  Yu-Ming Kang ,  Yuan-Tung Dai

IPC分类号： H01L2100

CPC分类号： H01L29/66757 ,  H01L29/458 ,  H01L29/4908

摘要： A manufacturing method of a thin film transistor (TFT) having low serial impedance is described. The method uses a back-side exposure and uses the active area as a hard mask; therefore, photomask usage may be reduced. On the other hand, a Si-Ge layer is used to react with the conductive layer deposited thereon after for forming a Ge-salicide layer. The method may reduce the required temperature of forming a Ge-salicide layer and the serial impedance.

摘要翻译： 描述具有低串联阻抗的薄膜晶体管（TFT）的制造方法。 该方法使用背面曝光，并使用有源区域作为硬掩模; 因此，可以减少光掩模的使用。 另一方面，在形成锗硅化物层之后，使用Si-Ge层与其上沉积的导电层反应。 该方法可以降低形成锗硅化物层所需的温度和串联阻抗。