VCSEL semiconductor devices with mode control
    1.
    发明申请
    VCSEL semiconductor devices with mode control 审中-公开
    VCSEL半导体器件具有模式控制

    公开(公告)号:US20070217472A1

    公开(公告)日:2007-09-20

    申请号:US11374676

    申请日:2006-03-14

    IPC分类号: H01S5/00

    摘要: A surface emitting laser having a substrate with top and bottom surfaces; a first stack of mirror layers of alternating indices of refraction located upon the top surface of the substrate; and active layer disposed over the first stack; a second stack of mirror layers of alternating indices of refraction disposed over the active layer and a recessed portion located centrally in the second stack extending through at least some of the second stack of mirror layers for improving the spectral width characteristic of the laser.

    摘要翻译: 一种表面发射激光器,具有具有顶表面和底表面的基底; 位于衬底顶表面上的交替折射率的第一层反射镜层; 以及设置在所述第一堆叠上的有源层; 设置在有源层上方的交替折射率的第二层反射镜层和位于第二层叠中心的凹陷部分延伸穿过第二层反射镜层中的至少一些,以改善激光器的光谱宽度特性。

    Passivation of Vertical Cavity Surface Emitting Lasers
    2.
    发明申请
    Passivation of Vertical Cavity Surface Emitting Lasers 审中-公开
    垂直腔表面发射激光器的钝化

    公开(公告)号:US20090041074A1

    公开(公告)日:2009-02-12

    申请号:US11835834

    申请日:2007-08-08

    申请人: Nein-Yi Li

    发明人: Nein-Yi Li

    IPC分类号: H01S5/02 H01L21/02

    摘要: A vertical cavity surface emitting laser including a substrate, a plurality of epitaxial layers formed on the substrate as an epitaxial stack, and a passivation layer at least partly covering the epitaxial stack including a plurality of sublayers at least some of which are composed of different materials. The composition and thicknesses of the sublayers are chosen to minimise the overall stress of the passivation layer and thereby to increase a mean time before the vertical surface emitting laser fails.

    摘要翻译: 包括衬底的垂直腔表面发射激光器,作为外延层叠的衬底上形成的多个外延层,以及至少部分地覆盖外延层的钝化层,其包括多个子层,其中至少一些由不同的材料组成 。 选择子层的组成和厚度以使钝化层的总应力最小化,从而增加在垂直表面发射激光器失效之前的平均时间。

    VCSEL semiconductor device
    3.
    发明授权
    VCSEL semiconductor device 有权
    VCSEL半导体器件

    公开(公告)号:US08189642B1

    公开(公告)日:2012-05-29

    申请号:US12710173

    申请日:2010-02-22

    IPC分类号: H01S5/00

    摘要: A vertical surface emitting laser having a mesa structure formed with sloping side walls. A passivation layer including at least two sublayers at least partially covers the mesa structure. The at least two sublayers have differing stress components arranged to at least partially counter each other. By making the mesa structure with sloping side walls, the deposition of the passivation layer in such a way as to minimize the net stress of the passivation layer is facilitated. In addition, the mesa structure has a first stack of mirror layers comprising a semiconductor material doped with a first dopant and having first peripheral oxidized portions extending a first distance into said first stack, and a second stack of mirror layers comprising a semiconductor material doped with a second dopant and having second peripheral oxidized portions extending a second distance into said second stack, wherein the first distance is different from the second distance. By controlling the first distance and the second distance appropriately, the internal stress in the mesa structure can be reduced.

    摘要翻译: 具有形成有倾斜侧壁的台面结构的垂直表面发射激光器。 包括至少两个子层的钝化层至少部分地覆盖台面结构。 至少两个子层具有不同的应力分量,其布置成至少部分地相互对抗。 通过使具有倾斜侧壁的台面结构,钝化层的沉积以使钝化层的净应力最小化的方式变得容易。 此外,台面结构具有包括掺杂有第一掺杂剂的半导体材料的第一层反射镜层,并且具有第一距离延伸到所述第一堆叠中的第一外围氧化部分,以及第二层反射镜层,其包括掺杂有 第二掺杂剂并且具有将第二距离延伸到所述第二堆叠中的第二外围氧化部分,其中所述第一距离与所述第二距离不同。 通过适当地控制第一距离和第二距离,可以减小台面结构中的内部应力。

    Npn double heterostructure bipolar transistor with ingaasn base region
    4.
    发明授权
    Npn double heterostructure bipolar transistor with ingaasn base region 有权
    Npn双异质结双极晶体管,具有基极区

    公开(公告)号:US06765242B1

    公开(公告)日:2004-07-20

    申请号:US09547152

    申请日:2000-04-11

    IPC分类号: H01L31072

    摘要: An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, Von, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.

    摘要翻译: 公开了一种NPN双异质结双极晶体管(DHBT),其具有包含夹在n型掺杂集电极和发射极区之间的p型掺杂的砷化镓镓(InGaAsN)层的基极区。 使用InGaAsN作为基极区域会降低晶体管导通电压Von,从而降低器件内的功耗。 具有用于形成低功率电子电路的应用的NPN晶体管形成在砷化镓(GaAs)衬底上,并且可以在商业GaAs铸造厂制造。 还公开了制造NPN晶体管的方法。