公开(公告)号：US06223299B1

公开(公告)日：2001-04-24

申请号：US09072418

申请日：1998-05-04

申请人： Douglas Craig Bossen ,  Charles Andrew McLaughlin ,  Danny Marvin Neal ,  James Otto Nicholson ,  Steven Mark Thurber

发明人： Douglas Craig Bossen ,  Charles Andrew McLaughlin ,  Danny Marvin Neal ,  James Otto Nicholson ,  Steven Mark Thurber

IPC分类号： G06F1100

CPC分类号： G06F11/0772 ,  G06F11/0745 ,  G06F11/0793

摘要： Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity of zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.

摘要翻译： 设备选择每个I / O设备的线路分别插入PCI主机桥，以便在PCI总线上出现错误时，可能会将故障设备的设备号记录在错误寄存器中。 在错误寄存器复位之前，后续的加载和存储操作将被延迟，直到可以针对错误寄存器检查主体设备的设备编号。 如果主机设备是先前发生故障的设备，则通过强制坏的奇偶校验或归零所有字节使能来防止对该设备的加载/存储操作完成。 通过强制零字节的不良奇偶使能，I / O设备将通过激活其设备选择行来响应加载或存储请求，但不接受存储数据。 允许对未登录在错误寄存器中的设备进行操作，正常情况下，正常情况下进行加载存储操作。 因此，正常的系统操作不会受到影响，并且如果这种操作不会造成进一步的损坏，则允许错误恢复期间的操作进行。

公开(公告)号：US6134621A

公开(公告)日：2000-10-17

申请号：US092153

申请日：1998-06-05

申请人： Richard Allen Kelley ,  Danny Marvin Neal ,  James Otto Nicholson ,  Steven Mark Thurber

发明人： Richard Allen Kelley ,  Danny Marvin Neal ,  James Otto Nicholson ,  Steven Mark Thurber

IPC分类号： G06F13/14 ,  G06F13/40 ,  G06F13/00 ,  G06F1/08 ,  G06F13/38

CPC分类号： G06F13/4068

摘要： A method and apparatus are provided in which a control scheme is implemented to enable a PCI bus to operate more than two PCI slots into which PCI devices may be installed. The PCI slots are checked to determine if a PCI device is installed in the slots and the speed at which the installed PCI devices are capable of running. If any of the slots has a 33 MHz device installed in any of the slots, the system is enabled to run more than two slots, and all of the PCI devices will run at 33 MHz. When no 33 MHz cards or devices are installed in the PCI slots, and PCI devices are only installed in the first two slots, then the system is enabled to run only the first two slots at the speed of 66 MHz. In one alternative embodiment, a default configuration routine sets the PCI bus speed at one of the operating frequencies and modifies that default if it is determined during a system configuration cycle that another speed is more appropriate.

摘要翻译： 提供了一种方法和装置，其中实现控制方案以使得PCI总线能够操作可以安装PCI设备的两个以上PCI插槽。 检查PCI插槽以确定PCI设备是否安装在插槽中以及安装的PCI设备能够运行的速度。 如果任何插槽中的任何一个插槽中都安装了一个33 MHz器件，则系统可以运行多于两个插槽，所有PCI设备将以33 MHz运行。 当PCI插槽中没有安装33 MHz的卡或设备时，PCI设备仅安装在前两个插槽中，则系统只能以66 MHz的速度运行前两个插槽。 在一个替代实施例中，默认配置例程将PCI总线速度设置为工作频率之一，并且如果在系统配置周期期间确定另一个速度更合适，则修改该默认值。

公开(公告)号：US07113995B1

公开(公告)日：2006-09-26

申请号：US09692348

申请日：2000-10-19

申请人： Bruce Leroy Beukema ,  Danny Marvin Neal ,  Gregory Francis Pfister ,  Renato John Recio ,  Steven Mark Thurber

发明人： Bruce Leroy Beukema ,  Danny Marvin Neal ,  Gregory Francis Pfister ,  Renato John Recio ,  Steven Mark Thurber

IPC分类号： G06F15/16

CPC分类号： H04L63/10 ,  H04L63/08

摘要： A method in a node for managing authorized attempts to access the node. A packet is received from a source, wherein the packet includes a first key. A determination is made as to whether the first key matches a second key for the node. The packet is dropped without a response to the source if the first key does not match the second key. Information from the packet is stored in response to this absence of a match. The information is sent to a selected recipient in response to a selected event, which may be, for example, either immediately or in response to polling to see if the information is present.

摘要翻译： 用于管理访问节点的授权尝试的节点中的方法。 从源接收分组，其中分组包括第一密钥。 确定第一个密钥是否与节点的第二个密钥相匹配。 如果第一个密钥与第二个密钥不匹配，数据包将被丢弃而不对源进行响应。 来自数据包的信息被存储以响应于缺少匹配。 响应于所选择的事件将信息发送到所选择的接收者，所选择的事件可以是例如立即地或响应于轮询来查看信息是否存在。

公开(公告)号：US06823404B2

公开(公告)日：2004-11-23

申请号：US09766764

申请日：2001-01-23

申请人： Richard Louis Arndt ,  Danny Marvin Neal ,  Steven Mark Thurber

发明人： Richard Louis Arndt ,  Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： G06F300

CPC分类号： G06F13/28

摘要： A method, system, and apparatus for preventing input/output (I/O) adapters used by an operating system (OS) image, in a logically partitioned data processing system, from fetching or corrupting data from a memory location allocated to another OS image within the data processing system is provided. A hypervisor prevents transmission of data between an input/output adapter in one of the logical partitions and memory locations assigned to other logical partitions during a direct memory access (DMA) operation by assigning each of the input/output adapters a range of I/O bus DMA addresses. The I/O adapters (IOAs) are connected to PCI host bridges via terminal bridges. A single terminal bridge may support multiple IOAs, in which case every terminal bridge has a plurality of sets of range registers, each associated with a respective one of the IOAs to which it is connected. An arbiter is provided which selects one of the input/output adapters to use the PCI bus. The terminal bridge can examine the grant signals from the arbiter to the IOAs, to determine which set of range registers is to be used.

摘要翻译： 用于防止在逻辑分区的数据处理系统中由操作系统（OS）映像使用的输入/输出（I / O）适配器的方法，系统和装置从分配给另一个OS映像的存储器位置获取或破坏数据 在数据处理系统内提供。 虚拟机管理程序防止在直接存储器访问（DMA）操作期间通过分配每个输入/输出适配器一个I / O范围的逻辑分区之一和分配给其他逻辑分区的存储器位置之间的输入/输出适配器之间的数据传输 总线DMA地址。 I / O适配器（IOA）通过终端桥连接到PCI主机桥。 单个终端桥可以支持多个IOA，在这种情况下，每个终端桥具有多组范围寄存器，每个范围寄存器与其所连接的IOA中的相应一个相关联。 提供了一个仲裁器，其选择一个输入/输出适配器来使用PCI总线。 终端桥可以检查从仲裁器到IOA的授权信号，以确定要使用哪个范围寄存器组。

公开(公告)号：US06636947B1

公开(公告)日：2003-10-21

申请号：US09645177

申请日：2000-08-24

申请人： Danny Marvin Neal ,  Steven Mark Thurber

发明人： Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： G06F1212

CPC分类号： G06F12/0817 ,  G06F2212/621

摘要： A method and implementing computer system are provided which enable a process for implementing a coherency system for bridge-cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain. An extended architecture includes one or more host bridges. At least one of the host bridges is coupled to I/O adapter devices through a lower-level bus-to-bus bridge and one or more I/O busses. The host bridge maintains a buffer coherency directory and when Invalidate commands are received by the host bridge, the bridge buffers containing the referenced data are identified and the indicated data are invalidated.

摘要翻译： 提供了一种方法和实现的计算机系统，其使得能够实现用于桥接缓存数据的一致性系统的过程，所述数据由通常在系统一致性域外的适配器和适配器桥接电路访问。 扩展架构包括一个或多个主机桥。 主桥中的至少一个通过下层总线到总线桥和一个或多个I / O总线耦合到I / O适配器设备。 主机桥保持缓冲区一致性目录，当Host Bridge接收到Invalidate命令时，将标识包含引用数据的桥接缓冲区，并指示数据无效。

公开(公告)号：US06581129B1

公开(公告)日：2003-06-17

申请号：US09414339

申请日：1999-10-07

申请人： Pat Allen Buckland ,  Daniel Frank Moertl ,  Danny Marvin Neal ,  Steven Mark Thurber ,  Scott Michael Willenborg ,  Curtis Carl Wollbrink ,  Adalberto Guillermo Yanes

发明人： Pat Allen Buckland ,  Daniel Frank Moertl ,  Danny Marvin Neal ,  Steven Mark Thurber ,  Scott Michael Willenborg ,  Curtis Carl Wollbrink ,  Adalberto Guillermo Yanes

IPC分类号： G06F1336

CPC分类号： G06F13/4027

摘要： A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.

摘要翻译： 公开了PCI主机桥和相关联的使用方法。 PCI主机桥包括主机总线接口，I / O总线接口和PCI操作检测电路。 主机总线接口适用于与数据处理系统的主机总线进行通信，I / O总线接口适用于与PCI-X模式下工作的主PCI总线进行通信。 PCI操作检测电路适于检测可能从耦合到辅助PCI总线的PCI模式适配器发出的主PCI总线的PCI-X操作。 检测电路还适于响应于确定PCI-X操作可能源自于PCI而产生用于转发到主机总线的修改操作。 模式适配器。

公开(公告)号：US06457077B1

公开(公告)日：2002-09-24

申请号：US09329459

申请日：1999-06-10

申请人： Richard A. Kelley ,  Danny Marvin Neal ,  Steven Mark Thurber ,  Adalberto Guillermo Yanes

发明人： Richard A. Kelley ,  Danny Marvin Neal ,  Steven Mark Thurber ,  Adalberto Guillermo Yanes

IPC分类号： G06F1314

CPC分类号： G06F13/4059

摘要： A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device. In an illustrated embodiment, the amount of over-commitment is programmable and the amount of over-commitment to transaction requests may be automatically adjusted to optimize the information transfer in accordance with the particular system demands and current data transfer traffic levels.

摘要翻译： 提供了一种方法和实现系统，其中系统桥电路能够执行或过度提交来自用于信息传输的系统设备的事务请求，该信息传输超过桥电路的当前容量，以便在从指定目标返回时接收所请求的信息 设备如系统内存或其他系统设备。 交易请求沿着数据路径移动到指定的目标设备，并且所请求的信息在示例中返回到请求设备。 当所请求的信息被返回到请求桥接电路时，多个保持缓冲器通常已经被释放并且可用于接受并将该信息传递给请求设备。 在所示实施例中，过度承诺的量是可编程的，并且可以自动调整对交易请求的过度承诺的量，以根据特定系统需求和当前数据传输流量水平优化信息传递。

公开(公告)号：US06421756B1

公开(公告)日：2002-07-16

申请号：US09306200

申请日：1999-05-06

申请人： Richard A. Kelley ,  Danny Marvin Neal ,  Steven Mark Thurber

发明人： Richard A. Kelley ,  Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： G06F1340

CPC分类号： G06F13/4031 ,  G06F13/4059

摘要： A method and implementing computer system are provided in which bridge buffers are grouped together in a pool, and are dynamically assigned and unassigned to adapter devices as needed during information transfers. In an exemplary peripheral component interconnect (PCI) system embodiment, a PCI Host Bridge (PHB) is coupled to a first PCI bus and one of the devices of the first PCI bus is occupied by a PCI-PCI bridge (PPB) which couples the first PCI bus to a second PCI bus. An assignment of PHB buffers in the PHB is made relative to the number of PCI devices which are connected both directly and indirectly to the first PCI bus. Devices on both the first and second PCI busses are given approximately equal status in the buffer assignment process. Upon a completion of a data transfer to or from any one of the adapters, the freed-up buffers which were assigned to that particular adapter are dynamically reassigned to other adapters as needed to optimize use of all of the buffers in the PHB pool.

摘要翻译： 提供了一种方法和实现的计算机系统，其中桥接缓冲器被组合在一起在池中，并且在信息传输期间根据需要被动态分配和未分配给适配器设备。 在示例性外围组件互连（PCI）系统实施例中，PCI主机桥（PHB）被耦合到第一PCI总线，并且第一PCI总线的设备中的一个被PCI-PCI桥（PPB）占用，PCI桥PCI 第一个PCI总线到第二个PCI总线。 相对于直接和间接连接到第一PCI总线的PCI设备的数量，PHB中的PHB缓冲器的分配。 在第一和第二PCI总线上的设备在缓冲区分配过程中被赋予大致相等的状态。 在完成到任何一个适配器的数据传输之后，分配给该特定适配器的释放缓冲区根据需要动态地重新分配给其他适配器，以优化PHB池中所有缓冲区的使用。

公开(公告)号：US06304984B1

公开(公告)日：2001-10-16

申请号：US09162936

申请日：1998-09-29

申请人： Danny Marvin Neal ,  Steven Mark Thurber

发明人： Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： H02H305

CPC分类号： G06F11/221 ,  G06F11/2221

摘要： A host bridge having a plurality of pre-defined registers used for injecting errors to a selected device so that other devices are not affected and normal systems operations can continue is disclosed. In accordance with the method and system of the present invention, device select lines from each device are brought into the host bridge individually for determining if an error is to be injected to a selected device. First, a register or a bit in a register in the host bridge is matched against an incoming bus operation for the type of bus operation, a load or a store, to inject the error upon. Next, a register having an initial or random value within the host bridge indicates which occurrence of the operation to inject the error. If the value of the register indicates that an error is to be injected, the load or store operation is delayed by forcing zero byte enables until the device identifier of the selected device may be checked against a device register within the host bridge. If the device register indicates the selected device, a type of error indicated by an error register within the host bridge is injected to the selected device and the operation is restarted. Operations to devices, which are not logged in the device register, are permitted to proceed normally, as are bus operations for devices logged in the device register based on the status of the register indicating the occurrence.

摘要翻译： 具有多个预定义寄存器的主桥，其用于向所选择的设备注入错误以便其他设备不受影响并且正常的系统操作可以继续。 根据本发明的方法和系统，将来自每个设备的设备选择线分别引入主桥，以确定是否将错误注入到所选择的设备。 首先，在主桥中的寄存器中的寄存器或位被匹配用于总线操作类型，负载或存储器的输入总线操作以将错误注入。 接下来，在主桥内具有初始值或随机值的寄存器指示注入错误的操作的发生。 如果寄存器的值指示要注入错误，则通过强制零字节使能来延迟加载或存储操作，直到所选设备的设备标识符可以针对主桥内的设备寄存器进行检查。 如果设备寄存器指示所选设备，则将主桥内的错误寄存器指示的错误类型注入所选设备，并重新启动操作。 允许对设备寄存器中未登录的设备的操作正常进行，以及基于寄存器指示发生的状态的设备寄存器的总线操作。

公开(公告)号：US06301627B1

公开(公告)日：2001-10-09

申请号：US09216548

申请日：1998-12-18

申请人： Danny Marvin Neal ,  Steven Mark Thurber

发明人： Danny Marvin Neal ,  Steven Mark Thurber

IPC分类号： G06F1314

CPC分类号： G06F13/4027

摘要： A method and apparatus is provided in which I/O data is tagged to identify an ordering of data transfer requests relative to other data transfer requests. Write and Read transaction requests are tagged for ordering relative to previous write requests. Current read and write transaction requests are selectively allowed to bypass earlier write transaction requests which have been temporarily delayed in transfer. In one embodiment, the bypass occurs in a bridge buffer positioned between I/O devices and a system memory. In another embodiment, the methodology is applied where a split read or write transaction includes reserved bits in the attribute fields which are utilized to indicate if the transaction is allowed to bypass previous write transactions.

摘要翻译： 提供了一种方法和装置，其中I / O数据被标记以识别相对于其他数据传送请求的数据传送请求的顺序。 写入和读取事务请求被标记为相对于先前的写入请求进行排序。 选择性地允许当前的读写事务请求绕过传输中已被暂时延迟的较早的写事务请求。 在一个实施例中，旁路发生在位于I / O设备和系统存储器之间的桥接缓冲器中。 在另一个实施例中，应用该方法，其中分割读或写事务包括属性字段中的保留位，用于指示事务是否允许绕过先前的写事务。