公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

公开(公告)号：US06764947B1

公开(公告)日：2004-07-20

申请号：US10366801

申请日：2003-02-14

申请人： Darin Chan ,  Douglas J. Bonser ,  Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Philip A. Fisher

发明人： Darin Chan ,  Douglas J. Bonser ,  Marina V. Plat ,  Marilyn I. Wright ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Philip A. Fisher

IPC分类号： H01L214763

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139

摘要： A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.

摘要翻译： 在非晶碳硬掩模和待蚀刻的多晶硅层之间设置氧化硅应力释放部分以形成栅极线。 应力消除部分减轻硬掩模和多晶硅之间的应力，从而降低在多晶硅图案化之前硬掩模的分层的风险。 应力消除部分可以在图案化之前被修整，并且用作图案化多晶硅的蚀刻掩模。 在图案化应力释放部分之前，可以修剪硬掩模的无定形碳以实现栅极线宽度的进一步降低。

公开(公告)号：US06750127B1

公开(公告)日：2004-06-15

申请号：US10367407

申请日：2003-02-14

申请人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

发明人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

IPC分类号： H01L213205

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/0337

摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.

摘要翻译： 注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。 这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

公开(公告)号：US06812077B1

公开(公告)日：2004-11-02

申请号：US10299433

申请日：2002-11-19

申请人： Darin Chan ,  Douglas J. Bonser ,  Mark S. Chang

发明人： Darin Chan ,  Douglas J. Bonser ,  Mark S. Chang

IPC分类号： H01L2100

CPC分类号： H01L21/32105 ,  H01L21/28088 ,  H01L21/28123

摘要： Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the patterned feature from undercutting growth of reacted material. Alternatively, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line and gate insulator.

摘要翻译： 在蚀刻完全通过图案化的导电层之前终止栅极线的图案化。 然后在反应性气氛中使导电层的表面反应，除去反应的表面，产生窄的栅极线。 在反应期间由导电层的剩余部分提供的保护保护图案化特征的下角部不被反应材料的底切生长。 或者，栅极线从包括下导电层和上导电层的多层导电结构图案化，反应性气氛中的反应性比下层高。 上层被图案化，然后结构在反应性气氛中反应。 然后去除上层的反应部分，并且以自对准方式图案化下层，以完成栅极线和栅极绝缘体的形成。

公开(公告)号：US20050158963A1

公开(公告)日：2005-07-21

申请号：US10759207

申请日：2004-01-20

申请人： Darin Chan ,  Simon Chan ,  Angela Hui

发明人： Darin Chan ,  Simon Chan ,  Angela Hui

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76224

摘要： Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments include etching back a silicon oxide trench filled to a depth of about 200 Å to about 1,500 Å, and then stripping a silicon nitride polish stop layer leaving a substantially planarized surface, thereby improving the accuracy of subsequent gate electrode patterning and reducing stringers.

摘要翻译： 通过在去除抛光停止膜之前相对于抛光止挡膜选择性地蚀刻回介质沟槽填充物而形成具有最小化形貌的平坦化STI。 实施例包括将填充至大约至大约深度的氧化硅沟槽刻蚀，然后剥离留下基本平坦化表面的氮化硅抛光停止层，从而提高随后的栅电极图案化和减少桁条的精度。

公开(公告)号：US20060246707A1

公开(公告)日：2006-11-02

申请号：US11119660

申请日：2005-05-02

申请人： Darin Chan

发明人： Darin Chan

IPC分类号： H01L21/4763

CPC分类号： H01L21/0217 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203

摘要： An integrated circuit having a plurality of active areas separated from each other by a field region and a method for manufacturing the integrated circuit. A first polysilicon finger is formed over the first active area and the field region and a second polysilicon finger is formed over the second active area and the field region. A first dielectric layer is formed over the first active area and the field region and a second dielectric layer is formed over the second active area and the portion of the first dielectric layer over the field region. A first electrical interconnect is formed over and dielectrically isolated from the first polysilicon finger and a second electrical interconnect is formed over and dielectrically isolated from the second active area. The second electrical interconnect is electrically coupled to the second polysilicon finger.

摘要翻译： 具有通过场区域彼此分离的多个有源区域的集成电路和用于制造集成电路的方法。 在第一有源区域和场区域上形成第一多晶硅指状物，并且在第二有源区域和场区域上形成第二多晶硅指状物。 在第一有源区和场区上形成第一电介质层，并且第二介电层形成在场区上的第二有源区和第一电介质层的部分上。 第一电互连形成在第一多晶硅指状物的上并与之电介质隔离，并且第二电互连形成在第二有源区上并与之相互隔离。 第二电互连电连接到第二多晶硅指状物。

公开(公告)号：US20060208321A1

公开(公告)日：2006-09-21

申请号：US11306663

申请日：2006-01-05

申请人： Darin Chan ,  Simon Chan ,  Paul King

发明人： Darin Chan ,  Simon Chan ,  Paul King

IPC分类号： H01L29/94 ,  H01L23/48

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a suicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

摘要翻译： 集成电路设置有半导体衬底，当半导体衬底反应以形成这种硅化物时，半导体衬底被掺杂有一定类型的可氧化掺杂剂的分离类型的硅化物顶部表面的浓度。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 源极/漏极结在半导体衬底中。 硅化物在源极/漏极结上，掺杂剂分离到硅化物的顶表面。 分离的掺杂剂的顶表面上的掺杂剂被氧化以在硅化物之上形成氧化掺杂剂的绝缘层。 层间电介质在半导体衬底之上。 触点和连接点位于硅化物之上的氧化掺杂剂的绝缘层的层间电介质中。

公开(公告)号：US20060197154A1

公开(公告)日：2006-09-07

申请号：US11071375

申请日：2005-03-03

申请人： Mario Pelella ,  Darin Chan ,  Simon Chan

发明人： Mario Pelella ,  Darin Chan ,  Simon Chan

IPC分类号： H01L27/12

CPC分类号： H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor component having analog and logic circuit elements manufactured from an SOI substrate and a method for manufacturing the semiconductor component. An SOI substrate has a support wafer coupled to an active wafer through an insulating material. Openings are formed in the active wafer, extend through the insulating material, and expose portions of the support wafer. Epitaxial semiconductor material is grown on the exposed portions of the support wafer. Analog circuitry is manufactured from the epitaxially grown semiconductor material and high performance logic circuitry is manufactured from the active wafer. The processing steps for manufacturing the analog circuitry are decoupled from the steps for manufacturing the high performance logic circuitry. A substrate contact is made from a portion of the epitaxially grown semiconductor material that is electrically isolated from the portion in which the analog circuitry is manufactured.

摘要翻译： 具有由SOI衬底制造的模拟和逻辑电路元件的半导体元件和用于制造半导体元件的方法。 SOI衬底具有通过绝缘材料耦合到有源晶片的支撑晶片。 开口形成在有源晶片中，延伸穿过绝缘材料，并暴露支撑晶片的部分。 外延半导体材料在支撑晶片的暴露部分上生长。 模拟电路由外延生长的半导体材料制成，高性能逻辑电路由有源晶片制造。 用于制造模拟电路的处理步骤与用于制造高性能逻辑电路的步骤分离。 从与制造模拟电路的部分电隔离的外延生长的半导体材料的一部分制成衬底接触。