公开(公告)号：US06366984B1

公开(公告)日：2002-04-02

申请号：US09309726

申请日：1999-05-11

申请人： Douglas M. Carmean ,  Brent E. Lince

发明人： Douglas M. Carmean ,  Brent E. Lince

IPC分类号： G06F1208

CPC分类号： G06F12/0804 ,  G06F12/0831 ,  G06F12/0897

摘要： A write combining buffer that supports snoop requests includes a first cache memory and a second cache memory. The apparatus also includes a write combining buffer, coupled to the first and second cache memories, to combine data from a plurality of store operations. Each of the plurality of store operations is to at least a part of a cache line, and the write combining buffer can be snooped in response to requests initiated external to the apparatus.

摘要翻译： 支持窥探请求的写入组合缓冲器包括第一缓存存储器和第二高速缓冲存储器。 该装置还包括耦合到第一和第二高速缓存存储器的组合缓冲器，以组合来自多个存储操作的数据。 多个存储操作中的每一个都是高速缓存线的至少一部分，并且可以响应于在该设备外部发起的请求来窥探该写入组合缓冲器。

公开(公告)号：US06334171B1

公开(公告)日：2001-12-25

申请号：US09292323

申请日：1999-04-15

申请人： Dave L. Hill ,  Douglas M. Carmean ,  Brent E. Lince ,  Muntaquim F. Chowdhury

发明人： Dave L. Hill ,  Douglas M. Carmean ,  Brent E. Lince ,  Muntaquim F. Chowdhury

IPC分类号： G06F1208

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3851 ,  G06F12/0888

摘要： A system for write-combining uncacheable stores includes a memory order buffer, which receives first and second stores, and a data cache address and control, which receives the first and second stores from the memory order buffer. One of the memory order buffer and the data cache address and control determines whether the first and second stores are uncacheable and whether the first and second stores are contiguous in memory. If those conditions are satisfied, the data cache address and control write-combines the first and second stores before committing them to memory. The system may also apply additional conditions to determine whether the stores should be write-combined, for example requiring a minimum size for each store.

摘要翻译： 用于写入组合不可缓存存储的系统包括接收第一和第二存储的存储器顺序缓冲器以及从存储器顺序缓冲器接收第一和第二存储的数据高速缓存地址和控制。 存储器顺序缓冲器和数据高速缓存地址和控制之一确定第一和第二存储器是否不可缓存，以及存储器中第一和第二存储器是否连续。 如果满足这些条件，数据缓存地址和控制写入 - 将第一个和第二个存储合并到存储器之前。 系统还可以应用附加条件来确定商店是否应该被写入组合，例如对于每个商店需要最小尺寸。

公开(公告)号：US06370625B1

公开(公告)日：2002-04-09

申请号：US09474698

申请日：1999-12-29

申请人： Douglas M. Carmean ,  Harish Kumar ,  Brent E. Lince ,  Michael D. Upton ,  Zhongying Zhang

发明人： Douglas M. Carmean ,  Harish Kumar ,  Brent E. Lince ,  Michael D. Upton ,  Zhongying Zhang

IPC分类号： G06F1318

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3842

摘要： A method of controlling operations by one or more processors includes granting ownership of a memory location having data stored therein to a first processor and performing, in an atomic manner by the first processor, a read operation to load the data from the memory location to a register, a modify operation to modify the data in the register, and a write operation to store the data from the register to the memory location. The method also prevents other operations directed towards the data by a second processor while the read, modify, and write operations are performed by the first processor, and vice versa. Ownership of the memory location is released after performing the read, modify, and write operations so as to allow the first or second processors to perform subsequent atomic operations.

摘要翻译： 一种控制一个或多个处理器的操作的方法包括将具有其中存储的数据的存储器位置的所有权授予第一处理器，并以原子方式由第一处理器执行读取操作，以将数据从存储器位置加载到 注册，修改操作以修改寄存器中的数据，以及写入操作，以将数据从寄存器存储到存储器位置。 当读取，修改和写入操作由第一处理器执行时，该方法还防止由第二处理器指向数据的其他操作，反之亦然。 在执行读取，修改和写入操作之后释放内存位置的所有权，以便允许第一或第二处理器执行后续的原子操作。

公开(公告)号：US5526510A

公开(公告)日：1996-06-11

申请号：US315889

申请日：1994-09-30

申请人： Haitham Akkary ,  Mandar S. Joshi ,  Rob Murray ,  Brent E. Lince ,  Paul D. Madland ,  Andrew F. Glew ,  Glenn J. Hinton

发明人： Haitham Akkary ,  Mandar S. Joshi ,  Rob Murray ,  Brent E. Lince ,  Paul D. Madland ,  Andrew F. Glew ,  Glenn J. Hinton

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0859

摘要： The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back to main memory. Circuitry is provided for transferring a cache line from the fill buffer into the data cache banks while simultaneously transferring a victim cache line from the data cache banks into the write-back buffer. Such allows the overall replace operation to be performed in only a single clock cycle. In a particular implementation, the data cache unit is employed within a microprocessor capable of speculative and out-of-order processing of memory instructions. Moreover, the microprocessor is incorporated within a multiprocessor computer system wherein each microprocessor is capable of snooping the cache lines of data cache units of each other microprocessor. The data cache unit is also a non-blocking cache.

摘要翻译： 数据高速缓存单元包括单独的填充缓冲器和单独的回写缓冲器。 填充缓冲器存储用于转移到数据高速缓存单元的数据高速缓存组中的一个或多个高速缓存行。 回写缓冲器在回写到主存储器之前存储从数据高速缓冲存储器中逐出的单个高速缓存行。 提供电路用于将高速缓存行从填充缓冲器传送到数据高速缓存组，同时将受害缓存行从数据高速缓冲存储体传输到回写缓冲器。 这样允许整个替换操作仅在单个时钟周期中执行。 在特定实现中，在能够对存储器指令进行推测和无序处理的微处理器中采用数据高速缓存单元。 此外，微处理器并入多处理器计算机系统中，其中每个微处理器能够窥探每个其他微处理器的数据高速缓存单元的高速缓存行。 数据高速缓存单元也是非阻塞缓存。

公开(公告)号：US06378048B1

公开(公告)日：2002-04-23

申请号：US09190126

申请日：1998-11-12

申请人： Chinna Prudvi ,  Paul Breuder ,  Quinn W. Merrill ,  Derek Bachand ,  Harish kumar Kumar ,  Brent E. Lince

发明人： Chinna Prudvi ,  Paul Breuder ,  Quinn W. Merrill ,  Derek Bachand ,  Harish kumar Kumar ,  Brent E. Lince

IPC分类号： G06F1300

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state, a modified state, and an exclusive state. Based upon the names of these states, the disclosed methods and systems may be labeled “SLIME.” The method of cache coherency may include storing a copy of data in a cache and storing state information identifying the copy as being stored in one of the five above-mentioned states. In response to a snoop request related to the data, marking a status field indicative of the state of the data to represent that the data is shared without regard to the data's dirty status. The data eviction method includes storing data in a cache, storing a status field in association with the data, the status field having a first sub-field to indicate whether the data is dirty and a second sub-field to indicate whether the data is shared, when the data is to be evicted from the cache, testing the first sub-field field to determine whether the data is dirty and, if so, writing the data to another cache before evicting the data from the cache. The multi-layer cache system includes first and second caches provided in a layered arrangement with the second cache being in a higher layer than the first cache, each cache including cache entries adapted to store data and status fields associated with the data, the status field representing the state of the data, eviction logic in the first cache adapted to test the status field of a cache entry, and control logic adapted to output the contents of the cache entry to a cache entry in the second cache when the status field indicates that data in the cache entry is dirty.

摘要翻译： 公开了高速缓存一致性方法，数据驱逐方法和多级缓存系统。 数据副本可以采用共享状态，懒惰状态，无效状态，修改状态和独占状态的五种状态之一。 根据这些州的名称，所公开的方法和系统可以标记为“SLIME”。 高速缓存一致性的方法可以包括将数据副本存储在高速缓冲存储器中，并将识别复制件的状态信息存储为以上述五个状态之一存储。 响应于与数据相关的窥探请求，标记指示数据状态的状态字段以表示数据被共享而不考虑数据的脏状态。 数据驱逐方法包括将数据存储在高速缓存中，与数据相关联地存储状态字段，状态字段具有第一子字段以指示数据是否脏，还有第二子字段指示数据是否被共享 当数据要从缓存中逐出时，测试第一个子字段以确定数据是否是脏的，如果是这样，则在从缓存中取出数据之前将数据写入另一个高速缓存。 多层缓存系统包括以分层布置提供的第一和第二高速缓存，其中第二高速缓存处于比第一高速缓存更高的层中，每个高速缓存包括适于存储与数据相关联的数据和状态字段的高速缓存条目，状态字段 表示数据的状态，适于测试高速缓存条目的状态字段的第一高速缓存中的逐出逻辑以及适于在高速缓存条目的内容输出到第二高速缓存中的高速缓存条目的控制逻辑，当状态字段指示 缓存条目中的数据很脏。

公开(公告)号：US5680572A

公开(公告)日：1997-10-21

申请号：US680109

申请日：1996-07-15

申请人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

发明人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

IPC分类号： G06F12/08

CPC分类号： G06F12/0859

摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

摘要翻译： 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

公开(公告)号：US5671444A

公开(公告)日：1997-09-23

申请号：US731545

申请日：1996-10-15

申请人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

发明人： Haitham Akkary ,  Jeffrey M. Abramson ,  Andrew F. Glew ,  Glenn J. Hinton ,  Kris G. Konigsfeld ,  Paul D. Madland ,  Mandar S. Joshi ,  Brent E. Lince

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0859 ,  G06F12/0831

摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.

摘要翻译： 具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。 每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。 当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。 此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。 因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。