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    Narrow body field-effect transistor structures with free-standing extension regions
    2.
    发明授权
    Narrow body field-effect transistor structures with free-standing extension regions 有权
    具有独立扩展区域的窄体场效应晶体管结构

    公开(公告)号：US09048258B2

    公开(公告)日：2015-06-02

    申请号：US13611900

    申请日：2012-09-12

    申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

    发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

    IPC分类号： H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L29/785 ,  H01L29/78654

    摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.

    摘要翻译： 窄体FET，例如FinFET和触发器，与诸如平面体SiFET和平面部分耗尽SOI（PDSOI）FET的厚体器件相比，表现出优异的短沟道特性。 然而，窄体设备的一个常见问题是高串联电阻，通常会抵消短通道的好处。 高串联电阻是由于在SOI / BOX界面处的掺杂剂堆积或掺入到BOX中的掺杂物。 本公开描述了一种新颖的窄体装置几何形状，其预期将克服高串联电阻问题。

    Narrow body field-effect transistor structures with free-standing extension regions
    3.
    发明授权
    Narrow body field-effect transistor structures with free-standing extension regions 有权
    具有独立扩展区域的窄体场效应晶体管结构

    公开(公告)号：US08884370B2

    公开(公告)日：2014-11-11

    申请号：US13457748

    申请日：2012-04-27

    申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

    发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

    IPC分类号： H01L27/12 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/785 ,  H01L29/78654

    摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.

    摘要翻译： 窄体FET，例如FinFET和触发器，与诸如平面体SiFET和平面部分耗尽SOI（PDSOI）FET的厚体器件相比，表现出优异的短沟道特性。 然而，窄体设备的一个常见问题是高串联电阻，通常会抵消短通道的好处。 高串联电阻是由于在SOI / BOX界面处的掺杂剂堆积或掺入到BOX中的掺杂物。 本公开描述了一种新颖的窄体装置几何形状，其预期将克服高串联电阻问题。

    NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS
    4.
    发明申请
    NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS 有权
    具有自由扩展区域的窄体现场效应晶体管结构

    公开(公告)号：US20130285142A1

    公开(公告)日：2013-10-31

    申请号：US13457748

    申请日：2012-04-27

    申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

    发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Amlan Majumdar ,  Lidija Sekaric

    IPC分类号： H01L27/12 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/785 ,  H01L29/78654

    摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.

    摘要翻译： 窄体FET，例如FinFET和触发器，与诸如平面体SiFET和平面部分耗尽SOI（PDSOI）FET的厚体器件相比，表现出优异的短沟道特性。 然而，窄体设备的一个常见问题是高串联电阻，通常会抵消短通道的好处。 高串联电阻是由于在SOI / BOX界面处的掺杂剂堆积或掺入到BOX中的掺杂物。 本公开描述了一种新颖的窄体装置几何形状，其预期将克服高串联电阻问题。

    SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES
    6.
    发明申请
    SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES 审中-公开
    半导体线阵列变阻器结构

    公开(公告)号：US20130316512A1

    公开(公告)日：2013-11-28

    申请号：US13495148

    申请日：2012-06-13

    申请人： Oki Gunawan ,  Amlan Majumdar ,  Katherine L. Saenger

    发明人： Oki Gunawan ,  Amlan Majumdar ,  Katherine L. Saenger

    IPC分类号： H01L49/02

    CPC分类号： H01L28/40 ,  H01L27/0203 ,  H01L27/0808 ,  H01L29/93

    摘要： Semiconductor variable capacitor (varactor) devices are provided, which are formed with an array of radial p-n junction structures to provide improved dynamic range and sensitivity. For example, a semiconductor varactor device includes a doped semiconductor substrate having first and second opposing surfaces and an array of pillar structures formed on the first surface of the doped semiconductor substrate. Each pillar structure includes a radial p-n junction structure. A first metallic contact layer is conformally formed over the array of pillar structures on the first surface of the doped semiconductor substrate. A second metallic contact layer formed on the second surface of the doped semiconductor substrate. An insulating layer is formed on the doped semiconductor substrate surrounding the array of pillar structures.

    摘要翻译： 提供半导体可变电容器（变容二极管）器件，其形成有径向p-n结结构的阵列，以提供改善的动态范围和灵敏度。 例如，半导体变容二极管器件包括具有第一和第二相对表面的掺杂半导体衬底和形成在掺杂半导体衬底的第一表面上的柱结构阵列。 每个柱结构包括径向p-n结结构。 第一金属接触层在掺杂半导体衬底的第一表面上的柱结构阵列上共形地形成。 形成在掺杂半导体衬底的第二表面上的第二金属接触层。 在包围柱结构阵列的掺杂半导体衬底上形成绝缘层。

    SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES
    7.
    发明申请
    SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES 审中-公开

    公开(公告)号：US20130313683A1

    公开(公告)日：2013-11-28

    申请号：US13479871

    申请日：2012-05-24

    申请人： Oki Gunawan ,  Amlan Majumdar ,  Katherine L. Saenger

    发明人： Oki Gunawan ,  Amlan Majumdar ,  Katherine L. Saenger

    IPC分类号： H01L29/93

    CPC分类号： H01L28/40 ,  H01L27/0203 ,  H01L27/0808 ,  H01L29/93

    摘要： Semiconductor variable capacitor (varactor) devices are provided, which are formed with an array of radial p-n junction structures to provide improved dynamic range and sensitivity. For example, a semiconductor varactor device includes a doped semiconductor substrate having first and second opposing surfaces and an array of pillar structures formed on the first surface of the doped semiconductor substrate. Each pillar structure includes a radial p-n junction structure. A first metallic contact layer is conformally formed over the array of pillar structures on the first surface of the doped semiconductor substrate. A second metallic contact layer formed on the second surface of the doped semiconductor substrate. An insulating layer is formed on the doped semiconductor substrate surrounding the array of pillar structures.

    Nanowire tunnel field effect transistors
    9.
    发明授权
    Nanowire tunnel field effect transistors 有权
    纳米线隧道场效应晶体管

    公开(公告)号：US08723162B2

    公开(公告)日：2014-05-13

    申请号：US13541022

    申请日：2012-07-03

    申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L29/06

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

    摘要： A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

    摘要翻译： 纳米线隧道场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有第一远端和第二远端的硅部分，硅部分被围绕硅部分周向设置的栅极结构围绕，漏极区域包括 从第一远端延伸的掺杂硅部分，布置在沟道区域中的掺杂硅部分的一部分，由硅部分的第二远端限定的空腔和栅极结构的内径，以及源区域， 从空腔中的硅部分的第二远端外延延伸的掺杂外延硅部分，第一焊盘区域和硅衬底的一部分。

    NANOWIRE FLOATING GATE TRANSISTOR
    10.
    发明申请
    NANOWIRE FLOATING GATE TRANSISTOR 有权
    NANOWIRE浮动门极晶体管

    公开(公告)号：US20130175597A1

    公开(公告)日：2013-07-11

    申请号：US13344517

    申请日：2012-01-05

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L29/788 ,  H01L21/28

    CPC分类号： G11C11/5671 ,  H01L21/28273 ,  H01L29/0673 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

    摘要： A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.

    摘要翻译： 浮栅晶体管，存储单元及其制造方法。 浮栅晶体管包括一个或多个基本上圆柱形的选通线。 浮置栅极晶体管包括至少部分地覆盖选通导线的第一栅极电介质层。 浮置栅极晶体管还包括不连续地布置在第一栅极介电层上的多个栅极晶体。 浮栅晶体管还包括覆盖多个栅极晶体和第一栅极介电层的第二栅极电介质层。