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    SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES
    1.
    发明申请
    SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES 审中-公开

    公开(公告)号：US20130313683A1

    公开(公告)日：2013-11-28

    申请号：US13479871

    申请日：2012-05-24

    申请人： Oki Gunawan ,  Amlan Majumdar ,  Katherine L. Saenger

    发明人： Oki Gunawan ,  Amlan Majumdar ,  Katherine L. Saenger

    IPC分类号： H01L29/93

    CPC分类号： H01L28/40 ,  H01L27/0203 ,  H01L27/0808 ,  H01L29/93

    摘要： Semiconductor variable capacitor (varactor) devices are provided, which are formed with an array of radial p-n junction structures to provide improved dynamic range and sensitivity. For example, a semiconductor varactor device includes a doped semiconductor substrate having first and second opposing surfaces and an array of pillar structures formed on the first surface of the doped semiconductor substrate. Each pillar structure includes a radial p-n junction structure. A first metallic contact layer is conformally formed over the array of pillar structures on the first surface of the doped semiconductor substrate. A second metallic contact layer formed on the second surface of the doped semiconductor substrate. An insulating layer is formed on the doped semiconductor substrate surrounding the array of pillar structures.

    SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES
    2.
    发明申请
    SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES 审中-公开
    半导体线阵列变阻器结构

    公开(公告)号：US20130316512A1

    公开(公告)日：2013-11-28

    申请号：US13495148

    申请日：2012-06-13

    申请人： Oki Gunawan ,  Amlan Majumdar ,  Katherine L. Saenger

    发明人： Oki Gunawan ,  Amlan Majumdar ,  Katherine L. Saenger

    IPC分类号： H01L49/02

    CPC分类号： H01L28/40 ,  H01L27/0203 ,  H01L27/0808 ,  H01L29/93

    摘要： Semiconductor variable capacitor (varactor) devices are provided, which are formed with an array of radial p-n junction structures to provide improved dynamic range and sensitivity. For example, a semiconductor varactor device includes a doped semiconductor substrate having first and second opposing surfaces and an array of pillar structures formed on the first surface of the doped semiconductor substrate. Each pillar structure includes a radial p-n junction structure. A first metallic contact layer is conformally formed over the array of pillar structures on the first surface of the doped semiconductor substrate. A second metallic contact layer formed on the second surface of the doped semiconductor substrate. An insulating layer is formed on the doped semiconductor substrate surrounding the array of pillar structures.

    摘要翻译： 提供半导体可变电容器（变容二极管）器件，其形成有径向p-n结结构的阵列，以提供改善的动态范围和灵敏度。 例如，半导体变容二极管器件包括具有第一和第二相对表面的掺杂半导体衬底和形成在掺杂半导体衬底的第一表面上的柱结构阵列。 每个柱结构包括径向p-n结结构。 第一金属接触层在掺杂半导体衬底的第一表面上的柱结构阵列上共形地形成。 形成在掺杂半导体衬底的第二表面上的第二金属接触层。 在包围柱结构阵列的掺杂半导体衬底上形成绝缘层。

    Germanium-containing release layer for transfer of a silicon layer to a substrate
    3.
    发明授权
    Germanium-containing release layer for transfer of a silicon layer to a substrate 有权
    含锗释放层，用于将硅层转移到基底

    公开(公告)号：US08933456B2

    公开(公告)日：2015-01-13

    申请号：US13616322

    申请日：2012-09-14

    申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

    发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger

    IPC分类号： H01L29/38 ,  H01L21/02 ,  H01L21/762

    CPC分类号： H01L21/0262 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/76254

    摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.

    摘要翻译： 含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。 含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。 任选地，可以在含锗层上生长或替代含锗层。 随后将至少部分结晶的硅层沉积在含锗层上。 手柄基板结合到至少部分结晶的硅层。 本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅 层。 去除复合衬底上任何剩余的含锗层。

    BEOL compatible FET structrure
    7.
    发明授权
    BEOL compatible FET structrure 有权
    BEOL兼容FET结构

    公开(公告)号：US08569803B2

    公开(公告)日：2013-10-29

    申请号：US13572742

    申请日：2012-08-13

    申请人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

    发明人： Christy S. Tyberg ,  Katherine L. Saenger ,  Jack O. Chu ,  Harold J. Hovel ,  Robert L. Wisnieff ,  Kerry Bernstein ,  Stephen W. Bedell

    IPC分类号： H01L29/76

    CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

    摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

    GERMANIUM-CONTAINING RELEASE LAYER FOR TRANSFER OF A SILICON LAYER TO A SUBSTRATE
    8.
    发明申请
    GERMANIUM-CONTAINING RELEASE LAYER FOR TRANSFER OF A SILICON LAYER TO A SUBSTRATE 有权
    用于将硅层转移到基板的含锗包装层

    公开(公告)号：US20130015455A1

    公开(公告)日：2013-01-17

    申请号：US13616322

    申请日：2012-09-14

    申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Davendra k. Sadana ,  Katherine L. Saenger

    发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Daniel A. Inns ,  Jeehwan Kim ,  Davendra k. Sadana ,  Katherine L. Saenger

    IPC分类号： H01L29/38

    CPC分类号： H01L21/0262 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/76254

    摘要： A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer. Any remaining germanium-containing layer on the composite substrate is removed.

    摘要翻译： 含锗层沉积在单一晶体体硅衬底上，包括足以以原子浓度掺入1％-50％的氧的氧分压水平。 含锗层的厚度优选被限制以保持与底层硅衬底的一定程度的外延对准。 任选地，可以在含锗层上生长或替代含锗层。 随后将至少部分结晶的硅层沉积在含锗层上。 手柄基板结合到至少部分结晶的硅层。 本体硅衬底，含锗层，至少部分结晶的硅层和处理衬底的组件在含锗层内被切割以提供复合衬底，该复合衬底包括处理衬底和至少部分结晶的硅 层。 去除复合衬底上任何剩余的含锗层。