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1.发明授权Narrow body field-effect transistor structures with free-standing extension regions 有权具有独立扩展区域的窄体场效应晶体管结构公开(公告)号：US09048258B2
公开(公告)日：2015-06-02
申请号：US13611900
申请日：2012-09-12
IPC分类号： H01L21/265 , H01L29/78 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/785 , H01L29/78654
摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.
摘要翻译： 窄体FET，例如FinFET和触发器，与诸如平面体SiFET和平面部分耗尽SOI（PDSOI）FET的厚体器件相比，表现出优异的短沟道特性。 然而，窄体设备的一个常见问题是高串联电阻，通常会抵消短通道的好处。 高串联电阻是由于在SOI / BOX界面处的掺杂剂堆积或掺入到BOX中的掺杂物。 本公开描述了一种新颖的窄体装置几何形状，其预期将克服高串联电阻问题。
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2.发明授权Narrow body field-effect transistor structures with free-standing extension regions 有权具有独立扩展区域的窄体场效应晶体管结构公开(公告)号：US08884370B2
公开(公告)日：2014-11-11
申请号：US13457748
申请日：2012-04-27
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/785 , H01L29/78654
摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.
摘要翻译： 窄体FET，例如FinFET和触发器，与诸如平面体SiFET和平面部分耗尽SOI（PDSOI）FET的厚体器件相比，表现出优异的短沟道特性。 然而，窄体设备的一个常见问题是高串联电阻，通常会抵消短通道的好处。 高串联电阻是由于在SOI / BOX界面处的掺杂剂堆积或掺入到BOX中的掺杂物。 本公开描述了一种新颖的窄体装置几何形状，其预期将克服高串联电阻问题。
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3.发明申请NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS 有权具有自由扩展区域的窄体现场效应晶体管结构公开(公告)号：US20130285142A1
公开(公告)日：2013-10-31
申请号：US13457748
申请日：2012-04-27
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/785 , H01L29/78654
摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.
摘要翻译： 窄体FET，例如FinFET和触发器，与诸如平面体SiFET和平面部分耗尽SOI（PDSOI）FET的厚体器件相比，表现出优异的短沟道特性。 然而，窄体设备的一个常见问题是高串联电阻，通常会抵消短通道的好处。 高串联电阻是由于在SOI / BOX界面处的掺杂剂堆积或掺入到BOX中的掺杂物。 本公开描述了一种新颖的窄体装置几何形状，其预期将克服高串联电阻问题。
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公开(公告)号：US20130285126A1
公开(公告)日：2013-10-31
申请号：US13611900
申请日：2012-09-12
IPC分类号： H01L29/78 , H01L21/265
CPC分类号： H01L29/66772 , H01L29/785 , H01L29/78654
摘要： Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.
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公开(公告)号：US20110012177A1
公开(公告)日：2011-01-20
申请号：US12505603
申请日：2009-07-20
申请人： Dureseti Chidambarrao , Oki Gunawan , Xiao Hu Liu , Amlan Majumdar , Lidija Sekaric , Jeffrey W. Sleight
发明人： Dureseti Chidambarrao , Oki Gunawan , Xiao Hu Liu , Amlan Majumdar , Lidija Sekaric , Jeffrey W. Sleight
IPC分类号： H01L29/775 , H01L21/335
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/775 , H01L29/7843
摘要： A structure and a method for a semiconductor including a nanostructure semiconductor channel. The semiconductor may include a dielectric and an electrode, the electrode attached to the dielectric, a semiconductor channel may be disposed proximate to the dielectric, wherein the semiconductor channel has an electric mobility and is configured to have at least one dimension, and wherein the dielectric may be configured to apply a force at the at least one dimension.
摘要翻译： 一种包括纳米结构半导体通道的半导体的结构和方法。 半导体可以包括电介质和电极，附着到电介质的电极，半导体沟道可以靠近电介质设置，其中半导体沟道具有电迁移率，并且被配置为具有至少一个维度，并且其中电介质 可以被配置为在至少一个维度施加力。
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公开(公告)号：US08940548B2
公开(公告)日：2015-01-27
申请号：US13552727
申请日：2012-07-19
申请人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
发明人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
IPC分类号： G01N33/552 , G01N33/543 , B82Y10/00 , H01L29/78
CPC分类号： G01N33/54373 , B82Y10/00 , G01N27/3276 , G01N27/4145 , G01N33/543 , H01L29/785 , Y10S977/721 , Y10S977/92 , Y10S977/953
摘要： A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current.
摘要翻译： 用于感测电解质中的生物分子的方法包括将包含硅翅片的传感器的栅极电介质表面暴露于电解质，其中所述栅极电介质表面包括电介质材料和被配置为与所述生物分子结合的抗体; 对浸在电解质中的电极施加栅极电压; 并测量在硅片中流动的漏极电流的变化; 以及基于漏极电流的变化确定存在于电解质中的生物分子的量。
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公开(公告)号：US08691675B2
公开(公告)日：2014-04-08
申请号：US12625835
申请日：2009-11-25
IPC分类号： H01L21/04
CPC分类号： H01L21/2254
摘要： A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.
摘要翻译： 用掺杂剂原子掺杂硅层的方法通常包括使掺杂剂前体的蒸气与存在于硅层上的氧化物和/或氢氧化物反应性位点反应以形成掺杂剂前体的自组装单层; 用水蒸汽水解掺杂剂前体的自组装单层以在掺杂剂前体上形成侧基羟基; 用氧化物层封闭自组装单层; 以及在有效地将掺杂剂原子从掺杂剂前体扩散到硅层中的温度下退火硅层。 可以以类似的方式形成另外的单层，由此提供受控的掺杂剂前体化合物的逐层气相沉积用于硅的受控掺杂。
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公开(公告)号：US08513642B2
公开(公告)日：2013-08-20
申请号：US13541857
申请日：2012-07-05
IPC分类号： H01L29/06
CPC分类号： H01L21/228 , H01L21/22 , H01L29/06
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.
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公开(公告)号：US08368125B2
公开(公告)日：2013-02-05
申请号：US12505580
申请日：2009-07-20
IPC分类号： H01L27/085
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/0673 , H01L29/517 , H01L29/518 , H01L29/7842 , H01L29/7845
摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
摘要翻译： 电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。 此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加 取决于通道长度相对于晶体结构的对准。 给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。
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公开(公告)号：US07989233B2
公开(公告)日：2011-08-02
申请号：US13004340
申请日：2011-01-11
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.
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