公开(公告)号：US06873010B2

公开(公告)日：2005-03-29

申请号：US10682430

申请日：2003-10-10

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce Bennett Doris ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Jack Allen Mandelman

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce Bennett Doris ,  Oleg Gluschenkov ,  Rajarao Jammy ,  Jack Allen Mandelman

IPC分类号： H01L21/8242 ,  H01L29/76

CPC分类号： H01L27/10876 ,  H01L27/10864 ,  H01L27/10891 ,  H01L27/10894

摘要： An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.

摘要翻译： 集成电路包括具有由最小光刻特征分隔的阵列晶体管和由扩散阻挡层封装的非硅化金属位线的存储单元，而高性能逻辑晶体管可以形成在同一芯片上而不损害包括有效通道在内的性能， /漏极接触电阻，用于控制短沟道效应的延伸和晕轮植入物以及与现有技术的栅介质厚度相当的具有高杂质浓度和相应薄的耗尽层厚度的双功函数半导体栅极。 该结构通过使用掩模或抗间隔物（优选易于平坦化的材料）开发不同材料的厚/高结构来实现，并且使用平坦化为不同材料的结构的高度的类似掩模以使基板和栅极注入分离 在逻辑晶体管中。

公开(公告)号：US6069022A

公开(公告)日：2000-05-30

申请号：US092413

申请日：1998-06-05

申请人： James Marc Leas ,  Jack Allen Mandelman

发明人： James Marc Leas ,  Jack Allen Mandelman

IPC分类号： H01L25/04 ,  H01L31/112 ,  H01L21/00 ,  H01L21/336

CPC分类号： H01L25/043 ,  H01L31/1126 ,  H01L2924/0002

摘要： An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.

摘要翻译： 光学FET包括堆叠在栅极上的一个或多个光响应二极管。 每个二极管包括平面（水平）结。 选择二极管的数量以实现期望的栅极到源极电位差。 电气连接将二极管连接到FET的源极。

公开(公告)号：US5643822A

公开(公告)日：1997-07-01

申请号：US370703

申请日：1995-01-10

申请人： Toshiharu Furukawa ,  Jack Allen Mandelman ,  William R. Tonti

发明人： Toshiharu Furukawa ,  Jack Allen Mandelman ,  William R. Tonti

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC分类号： H01L21/76237

摘要： A method for improving the subthreshold leakage characteristics of a trench-isolated FET device is described. This method involves first forming a vertical slot within a stack structure disposed on an oxide-covered silicon substrate, and then forming spacers on the sidewalls of the slot. A trench is then etched in the substrate. Removal of the spacers uncovers a horizontal ledge on the exposed surfaces of the oxide-covered substrate, adjacent the trench. The ledge is then perpendicularly implanted with a suitable dopant, thereby suppressing edge conduction in the device. Articles prepared by this method are also described.

摘要翻译： 描述了一种用于改善沟槽隔离FET器件的亚阈值泄漏特性的方法。 该方法包括首先在布置在氧化物覆盖的硅衬底上的堆叠结构内形成垂直槽，然后在槽的侧壁上形成间隔件。 然后在衬底中蚀刻沟槽。 间隔件的移除在相邻于沟槽的氧化物覆盖的衬底的暴露的表面上露出水平突出部。 然后用合适的掺杂剂垂直注入凸缘，从而抑制器件中的边缘传导。 还描述了通过该方法制备的制品。