-
公开(公告)号：US08119472B2
公开(公告)日：2012-02-21
申请号：US11757883
申请日：2007-06-04
IPC分类号： H01L21/8238
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。
-
公开(公告)号：US07198995B2
公开(公告)日：2007-04-03
申请号：US10733378
申请日：2003-12-12
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7842 , H01L29/78684
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material form a first island and second island at an pFET region and a nFET region, respectively. A tensile hard mask is formed on the first and the second island layer prior to forming finFETs. An Si epitaxial layer is grown on the sidewalls of the finFETs with the hard mask, now a capping layer which is under tension, preventing lateral buckling of the nFET fin.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料分别在pFET区和nFET区形成第一岛和第二岛。 在形成finFET之前，在第一和第二岛层上形成拉伸硬掩模。 在具有硬掩模的finFET的侧壁上生长Si外延层，现在是处于张力下的封盖层，防止nFET鳍的横向屈曲。
-
公开(公告)号：US07247534B2
公开(公告)日：2007-07-24
申请号：US10715400
申请日：2003-11-19
IPC分类号： H01L21/237 , H01L21/8238 , H01L21/336 , H01L21/331 , H01L21/20 , H01L21/76
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。
-
公开(公告)号：US07223994B2
公开(公告)日：2007-05-29
申请号：US10859736
申请日：2004-06-03
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L21/0336
CPC分类号： H01L29/78 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrate, a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.
摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含Si部分，衬底的含Si部分顶部的压缩层和半导体硅 层在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。
-
公开(公告)号：US08232153B2
公开(公告)日：2012-07-31
申请号：US11757874
申请日：2007-06-04
IPC分类号： H01L21/337 , H01L21/8238 , H01L29/00
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译： 提供半导体结构和制造方法。 制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。 第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。 在第一岛和第二岛上形成不同材料的层。 科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。 可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。
-
公开(公告)号：US07560328B2
公开(公告)日：2009-07-14
申请号：US11694373
申请日：2007-03-30
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate, a first layered stack atop the substrate, the first layered stack comprising a first Si-containing portion of the substrates a compressive layer atop the Si-containing portion of the substrate, and a semiconducting silicon layer atop the compressive layer; and a second layered stack atop the substrate, the second layered stack comprising a second-silicon containing layer portion of the substrate, a tensile layer atop the second Si-containing portion of the substrate, and a second semiconducting silicon-layer atop the tensile layer.
摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括衬底，在衬底顶部的第一层叠堆叠，第一层叠堆叠包括衬底的第一含硅部分，衬底的含Si部分顶部的压缩层，以及半导体硅层 在压缩层顶上; 以及在所述衬底顶部的第二层叠叠层，所述第二层叠堆叠包括所述衬底的第二硅含有层部分，在所述衬底的所述第二含Si部分顶部的拉伸层，以及在所述拉伸层顶部的第二半导体硅层 。
-
公开(公告)号：US07144767B2
公开(公告)日：2006-12-05
申请号：US10667601
申请日：2003-09-23
IPC分类号： H01L21/8249
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828
摘要： A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.
摘要翻译： 一种用于制造集成电路的方法，该集成电路包括通过用掩模覆盖p型场效应晶体管的多个半导体器件，包括n型场效应晶体管和p型场效应晶体管，并且氧化栅极多晶硅的一部分 的n型场效应晶体管，使得在n型场效应晶体管的沟道内形成拉伸机械应力。
-
8.发明授权公开(公告)号：US08067805B2
公开(公告)日：2011-11-29
申请号：US12132705
申请日：2008-06-04
IPC分类号： H01L21/70
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。
-
公开(公告)号：US20080230840A1
公开(公告)日：2008-09-25
申请号：US12132705
申请日：2008-06-04
IPC分类号： H01L49/00
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
-
10.发明授权公开(公告)号：US07402870B2
公开(公告)日：2008-07-22
申请号：US10711899
申请日：2004-10-12
IPC分类号： H01L29/76
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。
-
-
-
-
-
-
-
-
-
搜索结果
97 条记录 (耗时 0.022 秒)
