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    Optical proximity correction method and apparatus
    5.
    发明授权
    Optical proximity correction method and apparatus 失效
    光学邻近校正方法和装置

    公开(公告)号：US06269472B1

    公开(公告)日：2001-07-31

    申请号：US08991785

    申请日：1997-12-12

    申请人： Mario Garza ,  John V. Jensen ,  Nicholas K. Eib ,  Keith K. Chao

    发明人： Mario Garza ,  John V. Jensen ,  Nicholas K. Eib ,  Keith K. Chao

    IPC分类号： G03F900

    CPC分类号： G03F7/70441 ,  G03F1/36 ,  H01J37/3023 ,  H01J2237/31769

    摘要： Disclosed is a method for correcting a layout design using a design rule checker. The method includes providing a layout design file having the layout design that is to be corrected for optical proximity by the design rule checker. Providing a run set to the design rule checker. The run set includes a plurality of correction values that are used to correct a plurality of features of the layout design that have a selected space dimension. Identifying each of the plurality of features that have the selected space dimension. The method further includes correcting each of the plurality of features that have the selected space dimension with one correction value of the plurality of correction values of the run set. Preferably, the run set is generated from a correction table that has the plurality of correction values.

    摘要翻译： 公开了一种使用设计规则检查器来校正布局设计的方法。 该方法包括提供具有布局设计的布局设计文件，该布局设计将被设计规则检查器的光学邻近度校正。 为设计规则检查器提供运行集。 运行集合包括用于校正具有选定的空间维度的布局设计的多个特征的多个校正值。 识别具有所选择的空间维度的多个特征中的每一个。 该方法还包括用运行集合的多个校正值的一个校正值校正具有所选择的空间维度的多个特征中的每一个。 优选地，从具有多个校正值的校正表生成运行组。

    Performing optical proximity correction with the aid of design rule checkers
    6.
    发明授权
    Performing optical proximity correction with the aid of design rule checkers 失效
    借助设计规则检查器执行光学邻近校正

    公开(公告)号：US5900338A

    公开(公告)日：1999-05-04

    申请号：US912887

    申请日：1997-08-15

    申请人： Mario Garza ,  Nicholas K. Eib ,  John V. Jensen ,  Keith K. Chao

    发明人： Mario Garza ,  Nicholas K. Eib ,  John V. Jensen ,  Keith K. Chao

    IPC分类号： G03F7/20 ,  G03F9/00

    CPC分类号： G03F7/70483 ,  G03F1/36 ,  G03F7/70441

    摘要： A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

    摘要翻译： 公开了一种用于识别集成电路布局设计的区域的方法，其中光学邻近校正将是最有用的，然后仅在这些区域上进行光学邻近校正。 更具体地说，该方法包括以下步骤：（a）利用设计规则检查器分析集成电路布局设计，以定位满足预定准则的集成电路布局设计的特征; 和（b）对符合标准的特征进行光学邻近校正，以便产生掩模版设计。 设计规则检查器选择特征的标准包括图案上的外角，特征的内角，特征尺寸，特征形状和特征角度。

    Performing optical proximity correction with the aid of design rule checkers
    7.
    发明授权
    Performing optical proximity correction with the aid of design rule checkers 有权
    借助设计规则检查器执行光学邻近校正

    公开(公告)号：US06282696B1

    公开(公告)日：2001-08-28

    申请号：US09265510

    申请日：1999-03-09

    申请人： Mario Garza ,  Nicholas K. Eib ,  John V. Jensen ,  Keith K. Chao

    发明人： Mario Garza ,  Nicholas K. Eib ,  John V. Jensen ,  Keith K. Chao

    IPC分类号： G06F760

    CPC分类号： G03F7/70441

    摘要： A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

    摘要翻译： 公开了一种用于识别集成电路布局设计的区域的方法，其中光学邻近校正将是最有用的，然后仅在这些区域上进行光学邻近校正。 更具体地说，该方法包括以下步骤：（a）利用设计规则检查器分析集成电路布局设计，以定位满足预定准则的集成电路布局设计的特征; 和（b）对符合标准的特征进行光学邻近校正，以便产生掩模版设计。 设计规则检查器选择特征的标准包括图案上的外角，特征的内角，特征尺寸，特征形状和特征角度。

    Performing optical proximity correction with the aid of design rule checkers
    8.
    发明授权
    Performing optical proximity correction with the aid of design rule checkers 失效
    借助设计规则检查器执行光学邻近校正

    公开(公告)号：US5705301A

    公开(公告)日：1998-01-06

    申请号：US607398

    申请日：1996-02-27

    申请人： Mario Garza ,  Nicholas K. Eib ,  John V. Jensen ,  Keith K. Chao

    发明人： Mario Garza ,  Nicholas K. Eib ,  John V. Jensen ,  Keith K. Chao

    IPC分类号： G03F7/20 ,  G03F9/00

    CPC分类号： G03F7/70483 ,  G03F1/36 ,  G03F7/70441

    摘要： A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design role checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design role checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

    摘要翻译： 公开了一种用于识别集成电路布局设计的区域的方法，其中光学邻近校正将是最有用的，然后仅在这些区域上进行光学邻近校正。 更具体地说，该方法包括以下步骤：（a）利用设计角色检查器分析集成电路布局设计，以定位满足预定标准的集成电路布局设计的特征; 和（b）对符合标准的特征进行光学邻近校正，以便产生掩模版设计。 设计角色检查器选择特征的标准包括图案上的外角，特征的内角，特征尺寸，特征形状和特征角度。

    Optical proximity correction method and apparatus
    9.
    发明授权
    Optical proximity correction method and apparatus 失效
    光学邻近校正方法和装置

    公开(公告)号：US5723233A

    公开(公告)日：1998-03-03

    申请号：US607365

    申请日：1996-02-27

    申请人： Mario Garza ,  Nicholas K. Eib ,  Keith K. Chao

    发明人： Mario Garza ,  Nicholas K. Eib ,  Keith K. Chao

    IPC分类号： G03F1/00 ,  G03F7/20 ,  H01L21/027 ,  G03F9/00

    CPC分类号： G03F7/70441 ,  G03F1/36

    摘要： A photolithography optical proximity correction method for mask layouts (e.g., reticle masks) is disclosed. The method includes performing pattern recognition on a layout design to identify locations of feature edges with respect to other feature edges in the layout design. The method further includes obtaining an optical proximity correction for at least one of the feature edges by evaluating one or more non-linear mathematical expressions for optical proximity correction at the location of that edge with respect to other feature edges.

    摘要翻译： 公开了一种用于掩模布局（例如，掩模版掩模）的光刻光学邻近校正方法。 该方法包括在布局设计中执行模式识别，以在布局设计中识别特征边缘相对于其他特征边缘的位置。 该方法还包括通过评估在该边缘相对于其它特征边缘的位置处的光学邻近校正的一个或多个非线性数学表达式来获得对于特征边缘中的至少一个的光学邻近校正。

    Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate
    10.
    发明授权
    Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate 失效
    使用半导体衬底上的集成电路结构的对准过程，使用在衬底上的间隔开的测试场中的潜像的散射测量

    公开(公告)号：US06809824B1

    公开(公告)日：2004-10-26

    申请号：US10006398

    申请日：2001-11-30

    申请人： Colin D. Yates ,  Nicholas F. Pasch ,  Nicholas K. Eib

    发明人： Colin D. Yates ,  Nicholas F. Pasch ,  Nicholas K. Eib

    IPC分类号： G01B1100

    CPC分类号： G03F7/70633 ,  G03F7/70675 ,  H01L22/34

    摘要： A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of a first layer on a semiconductor substrate, forming a layer of photoresist over the first layer, forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry. In a preferred embodiment, the test pattern formed in each of the selected fields in the first layer comprises a pattern of parallel spaced apart lines, and the latent images formed in the portions of the photoresist layer in the selected fields above the test pattern in the first layer also comprises a pattern of parallel spaced part lines, with the two sets of lines interspaced between one another and generally parallel to one another to form a diffraction pattern.

    摘要翻译： 用于测量在半导体衬底上的集成电路结构的光致抗蚀剂层中的潜像与衬底上的下层中形成的测试图案的潜像的对准的方法包括以下步骤：在第一层的选定区域中形成测试图案 半导体衬底，在第一层上形成光致抗蚀剂层，在位于第一层的测试图案上的所选场域中的光致抗蚀剂层的部分中形成潜像; 并且使用散射测量在第一层的所选场域中的测试图案与光致抗蚀剂层中的上覆潜像的对准。 在优选实施例中，形成在第一层中的每个选定场中的测试图案包括平行间隔开的​​线的图案，并且在该测试图案上方的选定区域的光致抗蚀剂层的部分中形成的潜像 第一层还包括平行间隔的部分线的图案，其中两组线彼此间隔并且大体上彼此平行以形成衍射图案。