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17 条记录 (耗时 0.012 秒)

    Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench
    2.
    发明授权
    Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench 失效
    用于制造集成电路结构的方法，其包括通过在图案化沟槽中的种子层上的选择性沉积形成在半导体衬底上的局部互连

    公开(公告)号：US5670425A

    公开(公告)日：1997-09-23

    申请号：US552461

    申请日：1995-11-09

    申请人： Richard Schinella ,  Mahesh K. Sanganeria

    发明人： Richard Schinella ,  Mahesh K. Sanganeria

    IPC分类号： H01L21/768 ,  H01L21/441

    CPC分类号： H01L21/76879

    摘要： A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

    摘要翻译： 描述了包括由导电金属化合物形成的一个或多个导电互连的局部互连结构及其形成方法。 导电金属化合物被选择性地沉积在一个或多个沟槽中，其预先形成在符合导电互连的所需图案的构造中的绝缘层中。 首先在沟槽的表面上选择性地形成种子层，然后将导电金属化合物选择性地沉积在沟槽中的种子层上，而不是在绝缘层的暴露表面上沉积。

    Method of forming SiGe gate electrode
    4.
    发明授权
    Method of forming SiGe gate electrode 有权
    形成SiGe栅电极的方法

    公开(公告)号：US06730588B1

    公开(公告)日：2004-05-04

    申请号：US10026407

    申请日：2001-12-20

    申请人： Richard Schinella

    发明人： Richard Schinella

    IPC分类号： H01L213205

    CPC分类号： H01L21/2807 ,  H01L21/32055 ,  Y10S438/933

    摘要： The present invention provides a method of forming SiGe gate electrodes using a thin nucleation layer. A dielectric layer is formed on a semiconductor wafer and a thin silicon nucleation layer deposited on top of the dielectric layer. A SiGe conducting film is deposited on the patterned silicon layer. The ratio of germanium to silicon in the gaseous source mixture for the silicon and germanium layer is selected so that the SiGe conducting film deposits on the nucleation layer but fails to deposit on the dielectric.

    摘要翻译： 本发明提供使用薄的成核层形成SiGe栅电极的方法。 介电层形成在半导体晶片上，并且沉积在电介质层顶部的薄硅成核层。 SiGe导电膜沉积在图案化硅层上。 选择用于硅和锗层的气态源混合物中的锗与硅的比例，使得SiGe导电膜沉积在成核层上，但不能沉积在电介质上。

    Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench
    8.
    发明授权
    Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench 失效
    用于制造集成电路结构的方法，其包括通过在图案化沟槽中的种子层上的选择性沉积形成在半导体衬底上的局部互连

    公开(公告)号：US5895261A

    公开(公告)日：1999-04-20

    申请号：US873809

    申请日：1997-06-12

    申请人： Richard Schinella ,  Mahesh K. Sanganeria

    发明人： Richard Schinella ,  Mahesh K. Sanganeria

    IPC分类号： H01L21/768 ,  H01L21/441

    CPC分类号： H01L21/76879

    摘要： A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

    摘要翻译： 描述了包括由导电金属化合物形成的一个或多个导电互连的局部互连结构及其形成方法。 导电金属化合物被选择性地沉积在一个或多个沟槽中，其预先形成在符合导电互连的所需图案的构造中的绝缘层中。 首先在沟槽的表面上选择性地形成种子层，然后将导电金属化合物选择性地沉积在沟槽中的种子层上，而不是在绝缘层的暴露表面上沉积。

    Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
    9.
    发明授权
    Process for planarizing upper surface of damascene wiring structure for integrated circuit structures 有权
    用于集成电路结构的镶嵌线结构的上表面平面化处理

    公开(公告)号：US06881664B2

    公开(公告)日：2005-04-19

    申请号：US10614776

    申请日：2003-07-07

    申请人： Wilbur G. Catabay ,  Richard Schinella ,  Zhihai Wang ,  Wei-Jen Hsia

    发明人： Wilbur G. Catabay ,  Richard Schinella ,  Zhihai Wang ,  Wei-Jen Hsia

    IPC分类号： B23H5/08 ,  C23F4/00 ,  C25F3/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/7684 ,  B23H5/08 ,  C23F4/00 ,  C25F3/02 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32136

    摘要： A three step process for planarizing an integrated circuit structure comprising one or more dielectric layers having trench and/or via openings therein lined with a layer of electrically conductive barrier liner material and filled with copper filler material.Sufficient excess copper (formed over the barrier liner portions on the top surface of the dielectric layer) is removed in an initial chemical mechanical polish (CMP) step to provide a planarized copper layer with a global planarity of about 20 nm to about 30 nm. The remainder of the excess copper over the portion of the barrier liner material lying on the top surface of the dielectric layer is then removed by electropolishing the structure, in a second step, until all of the excess copper over the portion of the barrier liner material lying on the top surface of the dielectric layer is removed. In a third step, all remaining portions of the diffusion barrier liner on the upper surface of the low k dielectric layer are then removed using a dry etching process selective to copper and the dielectric layer until all of the portions of the barrier layer over the top surface of the dielectric layer are removed; whereby the integrated circuit structure may be planarized by removal of all of the copper layer and barrier layer from the top surface of the dielectric layer while inhibiting dishing and/or erosion of the surface of copper filler material in the opening, and without risking distortion and/or delamination by the harsh effects of excessive CMP processing.

    摘要翻译： 一种用于平面化集成电路结构的三步法，该集成电路结构包括其中具有沟槽和/或通孔开口的一个或多个电介质层，内衬有一层导电阻挡衬里材料并填充有铜填充材料。 在初始化学机械抛光（CMP）步骤中除去足够的过量铜（形成在电介质层的顶表面上的阻挡衬里部分上），以提供具有约20nm至约30nm的全局平面度的平坦化的铜层。 然后通过在第二步骤中电解抛光该结构，直到在阻挡衬里材料的部分上的所有过量的铜之前，将位于介电层顶表面上的阻挡衬里材料部分上的剩余的铜剩余部分除去 位于介电层的顶表面上被去除。 在第三步骤中，然后使用对铜和电介质层有选择性的干式蚀刻工艺去除低k电介质层的上表面上的扩散阻挡衬垫的所有剩余部分，直到阻挡层的所有部分超过顶部 去除电介质层的表面; 从而通过从电介质层的顶表面去除所有的铜层和阻挡层，同时抑制开口中铜填充材料的表面的凹陷和/或侵蚀，并且不会产生变形和风险，从而平面化集成电路结构 /或由于过度的CMP加工造成的恶劣影响而分层。

    Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
    10.
    发明授权
    Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning 有权
    用于集成电路结构的低k电介质复合层，其在金属线之间提供无空隙的低k介电材料，同时通过中毒减轻

    公开(公告)号：US06800940B2

    公开(公告)日：2004-10-05

    申请号：US10099641

    申请日：2002-03-15

    申请人： Wilbur G. Catabay ,  Richard Schinella

    发明人： Wilbur G. Catabay ,  Richard Schinella

    IPC分类号： H01L2348

    CPC分类号： H01L21/02126 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3146 ,  H01L21/31629 ,  H01L21/76801

    摘要： A composite layer of low k silicon oxide dielectric material is formed on an oxide layer of an integrated circuit structure on a semiconductor substrate having closely spaced apart metal lines thereon. The composite layer of low k silicon oxide dielectric material exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines, deposition rates in other regions comparable to standard k silicon oxide, and reduced via poisoning characteristics. The composite layer of low k silicon oxide dielectric material is formed by depositing, in high aspect ratio regions between closely spaced apart metal lines, a first layer of low k silicon oxide dielectric material exhibiting void-free deposition properties until the resulting deposition of low k silicon oxide dielectric material reaches the level of the top of the metal lines on the oxide layer. A second layer of low k silicon oxide dielectric material, having a faster deposition rate than the first layer, is then deposited over the first layer up to the desired overall thickness of the low k silicon oxide dielectric layer. In a preferred embodiment, the steps to form the resulting composite layer of low k silicon oxide dielectric material are all carried out in a single vacuum processing apparatus without removal of the substrate from the vacuum apparatus.

    摘要翻译： 在其上具有紧密间隔开的金属线的半导体衬底的集成电路结构的氧化物层上形成低k氧化硅电介质材料的复合层。 低k氧化硅电介质材料的复合层在紧密间隔开的金属线之间的高纵横比区域表现出无空隙的沉积性质，在其它区域的沉积速率与标准k氧化硅相当，并且通过中毒特性降低。 低k氧化硅电介质材料的复合层是通过在紧密间隔的金属线之间的高纵横比区域沉积出第一层低k氧化硅电介质材料而形成的，这表现出无空隙的沉积特性，直到沉积低k 氧化硅介电材料达到氧化物层上金属线顶部的高度。 然后，在第一层上沉积具有比第一层更快的沉积速率的第二层低k氧化硅介电材料，直到低k氧化硅介电层的期望总厚度。 在优选实施例中，形成低k氧化硅介电材料的所得复合层的步骤都在单个真空处理设备中进行，而不从真空设备中去除衬底。