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    Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate
    5.
    发明授权
    Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate 失效
    使用半导体衬底上的集成电路结构的对准过程，使用在衬底上的间隔开的测试场中的潜像的散射测量

    公开(公告)号：US06809824B1

    公开(公告)日：2004-10-26

    申请号：US10006398

    申请日：2001-11-30

    申请人： Colin D. Yates ,  Nicholas F. Pasch ,  Nicholas K. Eib

    发明人： Colin D. Yates ,  Nicholas F. Pasch ,  Nicholas K. Eib

    IPC分类号： G01B1100

    CPC分类号： G03F7/70633 ,  G03F7/70675 ,  H01L22/34

    摘要： A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of a first layer on a semiconductor substrate, forming a layer of photoresist over the first layer, forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry. In a preferred embodiment, the test pattern formed in each of the selected fields in the first layer comprises a pattern of parallel spaced apart lines, and the latent images formed in the portions of the photoresist layer in the selected fields above the test pattern in the first layer also comprises a pattern of parallel spaced part lines, with the two sets of lines interspaced between one another and generally parallel to one another to form a diffraction pattern.

    摘要翻译： 用于测量在半导体衬底上的集成电路结构的光致抗蚀剂层中的潜像与衬底上的下层中形成的测试图案的潜像的对准的方法包括以下步骤：在第一层的选定区域中形成测试图案 半导体衬底，在第一层上形成光致抗蚀剂层，在位于第一层的测试图案上的所选场域中的光致抗蚀剂层的部分中形成潜像; 并且使用散射测量在第一层的所选场域中的测试图案与光致抗蚀剂层中的上覆潜像的对准。 在优选实施例中，形成在第一层中的每个选定场中的测试图案包括平行间隔开的​​线的图案，并且在该测试图案上方的选定区域的光致抗蚀剂层的部分中形成的潜像 第一层还包括平行间隔的部分线的图案，其中两组线彼此间隔并且大体上彼此平行以形成衍射图案。

    System and method for performing optical proximity correction on the interface between optical proximity corrected cells
    6.
    发明授权
    System and method for performing optical proximity correction on the interface between optical proximity corrected cells 失效
    用于在光学邻近校正单元之间的接口上执行光学邻近校正的系统和方法

    公开(公告)号：US06425117B1

    公开(公告)日：2002-07-23

    申请号：US08937296

    申请日：1997-09-29

    申请人： Nicholas F. Pasch ,  Nicholas K. Eib ,  Colin D. Yates ,  Shumay Dou

    发明人： Nicholas F. Pasch ,  Nicholas K. Eib ,  Colin D. Yates ,  Shumay Dou

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068 ,  G03F1/36

    摘要： The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.

    摘要翻译： 该系统和方法通过在用于创建IC的单元格库上最初执行光学邻近校正来对集成电路（IC）掩模设计执行光学邻近校正。 预先测试的细胞被导入到面罩设计中。 所有细胞被放置在最小距离之间，以确保在完全集成在不同细胞中的元素之间不会发生邻近效应。 通过仅对在一个单元内未完全集成的那些组件（例如线）执行接近校正来对掩模设计执行一维光学邻近校正技术。

    Automating photolithography in the fabrication of integrated circuits
    7.
    再颁专利
    Automating photolithography in the fabrication of integrated circuits 有权
    在制造集成电路时自动化光刻

    公开(公告)号：USRE38900E1

    公开(公告)日：2005-11-29

    申请号：US09273171

    申请日：1999-03-19

    申请人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    发明人： Michael D. Rostoker ,  Nicholas F. Pasch ,  Ashok K. Kapoor

    IPC分类号： G03F7/20 ,  H01L21/66

    CPC分类号： G03F7/705 ,  G03F7/20 ,  G03F7/70433

    摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

    摘要翻译： 集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。 然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。 然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。 然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。 然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。 以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

    Use of silicon for integrated circuit device interconnection by direct writing of patterns therein
    9.
    发明授权
    Use of silicon for integrated circuit device interconnection by direct writing of patterns therein 失效
    通过在其中直接写入图案，将硅用于集成电路器件互连

    公开(公告)号：US5721150A

    公开(公告)日：1998-02-24

    申请号：US614024

    申请日：1996-03-12

    申请人： Nicholas F. Pasch

    发明人： Nicholas F. Pasch

    IPC分类号： H01L21/268 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/58 ,  H01L21/265

    CPC分类号： H01L23/573 ,  H01L21/2686 ,  H01L21/32155 ,  H01L21/76888 ,  H01L21/76894 ,  H01L2924/0002 ,  Y10S438/934

    摘要： An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon is deposited onto an integrated circuit face at low temperature. A Focused Ion Beam deposition system deposits dopant atoms into the deposited pure silicon in a desired pattern. The dopant atoms are then activated by heat from a focused laser beam which adiabatically anneals the specifically doped areas of the deposited silicon. The resulting annealed doped areas of the silicon have low resistance suitable for circuit conductors. The surrounding undoped silicon reins a high resistance and a good insulator.

    摘要翻译： 一种其中导电图案被写入集成电路中沉积的非晶硅或多晶硅并用于互连其中包含的电路元件的装置和方法。 基本上纯的非晶硅或多晶硅在低温下沉积到集成电路面上。 聚焦离子束沉积系统以期望的图案将掺杂剂原子沉积到沉积的纯硅中。 然后，掺杂剂原子被来自聚焦激光束的热激活，该激光束绝热地退火沉积的硅的特定掺杂区域。 所得到的退火掺杂区域的硅具有适合于电路导体的低电阻。 周围的未掺杂硅可以获得高电阻和良好的绝缘体。

    Process for mounting a semiconductor device to a circuit substrate
    10.
    发明授权
    Process for mounting a semiconductor device to a circuit substrate 失效
    将半导体器件安装到电路基板的工艺

    公开(公告)号：US5700715A

    公开(公告)日：1997-12-23

    申请号：US434276

    申请日：1995-05-03

    申请人： Nicholas F. Pasch

    发明人： Nicholas F. Pasch

    IPC分类号： H01L21/60 ,  H01L23/532 ,  H01L21/283 ,  H01L21/58

    CPC分类号： H01L24/81 ,  H01L23/53285 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3025

    摘要： A process for mounting one or more dies a substrate, such as by ball-bumps. In one embodiment, a thin layer of heat-reflective material, such as gold, is disposed over the surface of the die facing the substrate, to shield the substrate from heat generated by the die. Other embodiments are directed to "pillar" spacers formed on the surface of the die and/or the substrate to control the spacing therebetween. The pillars can be thermally-conductive or thermally non-conductive. Thermally-conductive pillars can be thermally isolated from the die or substrate by an insulating layer. Thermally-conductive pillars can be employed to extract heat from selected areas of a die, into selected lines or areas of the substrate, and the heat on the substrate can then be dissipated by a coolant. Lines on the substrate which are advertently heated by the die can be employed to limit the current of selected circuits on the semiconductor die.

    摘要翻译： 用于将一个或多个模具安装在基板上的方法，例如通过球凸块。 在一个实施例中，诸如金的薄层的热反射材料设置在面对基板的模具的表面上，以屏蔽基板免受由模具产生的热量。 其他实施例涉及形成在管芯和/或衬底的表面上的“柱”间隔件，以控制它们之间的间隔。 支柱可以是导热的或热不导电的。 导热柱可以通过绝缘层与管芯或衬底热隔离。 可以使用导热柱将热量从模具的选定区域提取到基板的选定的线或区域中，然后基板上的热量可以被冷却剂消散。 通过裸片通常加热的衬底上的线可用于限制半导体管芯上所选电路的电流。