Apparatus and method for positively and subtractively decoding addresses
on a bus
    1.
    发明授权
    Apparatus and method for positively and subtractively decoding addresses on a bus 失效
    用于对总线上的地址进行正负的解码的装置和方法

    公开(公告)号:US5864688A

    公开(公告)日:1999-01-26

    申请号:US684584

    申请日:1996-07-19

    IPC分类号: G06F13/36 G06F13/40 G06F12/00

    CPC分类号: G06F13/4045

    摘要: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

    摘要翻译: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连(PCI)总线传递到工业标准架构(ISA)总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 根据对接状态,由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

    Computer system utilizing two ISA busses coupled to a mezzanine bus
    2.
    发明授权
    Computer system utilizing two ISA busses coupled to a mezzanine bus 失效
    利用耦合到夹层总线的两条ISA总线的计算机系统

    公开(公告)号:US5781748A

    公开(公告)日:1998-07-14

    申请号:US671316

    申请日:1996-07-19

    IPC分类号: G06F13/40 H01J13/00

    CPC分类号: G06F13/4027

    摘要: A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.

    摘要翻译: 具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。 扩展基座和便携式部分都包括用于将周期从外围部件互连(PCI)总线传递到工业标准架构(ISA)总线的桥接电路。 该桥包括用于控制解码的内部设备和配置寄存器。 用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。 根据对接状态,由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

    Circuit for handling distributed arbitration in a computer system having
multiple arbiters
    3.
    发明授权
    Circuit for handling distributed arbitration in a computer system having multiple arbiters 失效
    用于在具有多个仲裁器的计算机系统中处理分布式仲裁的电路

    公开(公告)号:US5954809A

    公开(公告)日:1999-09-21

    申请号:US684412

    申请日:1996-07-19

    IPC分类号: G06F13/362 G06F13/368

    CPC分类号: G06F13/368

    摘要: An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

    摘要翻译: 一种用于具有多个仲裁器的计算机系统的仲裁方案,用于仲裁对多条总线的访问。 在优选实施例中,计算机系统被分为可拆卸笔记本电脑部分和通过共享PCI总线耦合的扩展基座单元。 计算机系统的两个部分中的每一个包括单独的PCI仲裁电路,用于从潜在的PCI和ISA总线主机仲裁PCI总线的请求。 包括在计算机系统的笔记本电脑部分内的是顶级仲裁器,其确定膝上型计算机或扩展基座单元中的PCI仲裁器是否可以访问PCI总线。 PCI仲裁器通常必须在运行一个周期之前从顶级仲裁器接收授权。 当笔记本电脑停靠时,顶级仲裁器基本上基于时间复用的方式在PCI仲裁器之间进行选择。 当扩展基座和笔记本电脑脱离时,顶级仲裁器授予公共汽车访问笔记本电脑PCI仲裁器的权限。

    Bus system for shadowing registers
    4.
    发明授权
    Bus system for shadowing registers 失效
    用于阴影寄存器的总线系统

    公开(公告)号:US06247087B1

    公开(公告)日:2001-06-12

    申请号:US09036634

    申请日:1998-03-06

    IPC分类号: G06F1300

    CPC分类号: G06F13/4027

    摘要: The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

    摘要翻译: 本发明涉及一种用于对共享共同地址的计算机系统的第一寄存器和第二寄存器的数据进行阴影化的系统和方法。 当总线代理对寄存器地址执行写入操作时,第一桥接电路的重试逻辑重试写入操作,并掩盖总线代理对总线的访问。 重试总线主机逻辑重新执行写入操作,响应于此,第二桥接电路对该重新运行写入操作进行减法解码并将数据传送到第二寄存器。 然后允许总线代理重试初始写操作,响应于此,第一桥电路对其进行重试写入操作,并将数据传送到第一寄存器。 因此,在第一和第二寄存器之间保持一致性。

    Bus system for shadowing registers
    7.
    发明授权
    Bus system for shadowing registers 失效
    用于阴影寄存器的总线系统

    公开(公告)号:US5793995A

    公开(公告)日:1998-08-11

    申请号:US684486

    申请日:1996-07-19

    IPC分类号: G06F13/40 G06F13/00

    CPC分类号: G06F13/4027

    摘要: The present invention relates to a system and method for shadowing data of a first register and a second register of a computer system that share a common address. When a bus agent runs a write operation to the register address, retry logic of a first bridge circuit retries the write operation and masks access by the bus agent to the bus. Retry bus master logic reruns the write operation, in response to which the second bridge circuit subtractively decodes the rerun write operation and transfers the data to the second register. The bus agent is then allowed to retry the initial write operation, in response to which the first bridge circuit positively decodes the retried write operation and transfers the data to the first register. Thus, coherency is preserved between the first and second registers.

    摘要翻译: 本发明涉及一种用于对共享共同地址的计算机系统的第一寄存器和第二寄存器的数据进行阴影化的系统和方法。 当总线代理对寄存器地址执行写入操作时,第一桥接电路的重试逻辑重试写入操作,并掩盖总线代理对总线的访问。 重试总线主机逻辑重新执行写入操作,响应于此,第二桥接电路对该重新运行写入操作进行减法解码并将数据传送到第二寄存器。 然后允许总线代理重试初始写操作,响应于此,第一桥电路对其进行重试写入操作,并将数据传送到第一寄存器。 因此,在第一和第二寄存器之间保持一致性。

    Presenting multi-function devices behind a switch hierarchy as a single function device
    8.
    发明授权
    Presenting multi-function devices behind a switch hierarchy as a single function device 失效
    将交换机层次结构后面的多功能设备呈现为单个功能设备

    公开(公告)号:US08782289B2

    公开(公告)日:2014-07-15

    申请号:US12996996

    申请日:2008-06-10

    IPC分类号: G06F3/00 G06F13/00 H04L12/28

    CPC分类号: H04L12/28 G06F13/4027

    摘要: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

    摘要翻译: 在一个实施例中,计算机系统包括至少一个主机节点,耦合到主机节点的至少一个输入/输出节点,经由交换机耦合到输入/输出节点的至少一个多功能设备,以及中间管理器 处理器包括用于阻止主机节点中用于交换机层级之后的多功能设备的枚举过程的逻辑,为与主机节点分离的管理器处理器中的多功能设备启动枚举过程,存储用于交换机的路由表 耦合到管理器处理器的存储器模块中的层次结构,并且在管理器处理器中将端点设备资源分配给主机节点。

    System and method for multi-host sharing of a single-host device
    10.
    发明授权
    System and method for multi-host sharing of a single-host device 有权
    用于单主机设备的多主机共享的系统和方法

    公开(公告)号:US08176204B2

    公开(公告)日:2012-05-08

    申请号:US11450491

    申请日:2006-06-09

    申请人: Dwight D. Riley

    发明人: Dwight D. Riley

    IPC分类号: G06F15/173

    摘要: The present disclosure describes a system and method for multi-host extension of a single-host device comprising a network switch fabric that comprises a rooted hierarchical bus, a first compute node coupled to the network switch fabric, and an input/output (I/O) node coupled to the network switch fabric, the I/O node comprising a network switch fabric interface and a real single-host device. The network switch fabric interface creates a first virtual device mapped to the real single-host device. The first virtual device allows the first compute node to access the real single-host device.

    摘要翻译: 本公开描述了一种用于单主机设备的多主机扩展的系统和方法,包括网络交换结构,该网络交换结构包括根分层总线,耦合到网络交换结构的第一计算节点,以及输入/输出(I / O)节点,所述I / O节点包括网络交换结构接口和真实的单主机设备。 网络交换矩阵接口创建映射到真实单主机设备的第一虚拟设备。 第一虚拟设备允许第一计算节点访问真实的单主机设备。