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    Presenting multi-function devices behind a switch hierarchy as a single function device
    2.
    发明授权
    Presenting multi-function devices behind a switch hierarchy as a single function device 失效
    将交换机层次结构后面的多功能设备呈现为单个功能设备

    公开(公告)号：US08782289B2

    公开(公告)日：2014-07-15

    申请号：US12996996

    申请日：2008-06-10

    申请人： David L. Matthews ,  Hubert E. Brinkmann ,  James Xuan Dinh ,  Dwight D. Riley ,  Paul V. Brownell

    发明人： David L. Matthews ,  Hubert E. Brinkmann ,  James Xuan Dinh ,  Dwight D. Riley ,  Paul V. Brownell

    IPC分类号： G06F3/00 ,  G06F13/00 ,  H04L12/28

    CPC分类号： H04L12/28 ,  G06F13/4027

    摘要： In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

    摘要翻译： 在一个实施例中，计算机系统包括至少一个主机节点，耦合到主机节点的至少一个输入/输出节点，经由交换机耦合到输入/输出节点的至少一个多功能设备，以及中间管理器 处理器包括用于阻止主机节点中用于交换机层级之后的多功能设备的枚举过程的逻辑，为与主机节点分离的管理器处理器中的多功能设备启动枚举过程，存储用于交换机的路由表 耦合到管理器处理器的存储器模块中的层次结构，并且在管理器处理器中将端点设备资源分配给主机节点。

    System and method for multi-host sharing of a single-host device
    3.
    发明授权
    System and method for multi-host sharing of a single-host device 有权
    用于单主机设备的多主机共享的系统和方法

    公开(公告)号：US08176204B2

    公开(公告)日：2012-05-08

    申请号：US11450491

    申请日：2006-06-09

    申请人： Dwight D. Riley

    发明人： Dwight D. Riley

    IPC分类号： G06F15/173

    CPC分类号： H04L45/00 ,  H04L49/10 ,  H04L49/102 ,  H04L49/15 ,  H04L49/25 ,  H04L49/358

    摘要： The present disclosure describes a system and method for multi-host extension of a single-host device comprising a network switch fabric that comprises a rooted hierarchical bus, a first compute node coupled to the network switch fabric, and an input/output (I/O) node coupled to the network switch fabric, the I/O node comprising a network switch fabric interface and a real single-host device. The network switch fabric interface creates a first virtual device mapped to the real single-host device. The first virtual device allows the first compute node to access the real single-host device.

    摘要翻译： 本公开描述了一种用于单主机设备的多主机扩展的系统和方法，包括网络交换结构，该网络交换结构包括根分层总线，耦合到网络交换结构的第一计算节点，以及输入/输出（I / O）节点，所述I / O节点包括网络交换结构接口和真实的单主机设备。 网络交换矩阵接口创建映射到真实单主机设备的第一虚拟设备。 第一虚拟设备允许第一计算节点访问真实的单主机设备。

    Point-to-point electrical loading for a multi-drop bus
    4.
    发明授权
    Point-to-point electrical loading for a multi-drop bus 失效
    多点总线的点对点电气负载

    公开(公告)号：US07099966B2

    公开(公告)日：2006-08-29

    申请号：US10184164

    申请日：2002-06-28

    申请人： Michael Y. Chan ,  Dwight D. Riley

    发明人： Michael Y. Chan ,  Dwight D. Riley

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4068

    摘要： A switching technique allows multiple interconnect bus devices to be connected to a single bus segment, even if the interconnect bus protocol only allows a one of the interconnect devices to be connected at any time. Each of the interconnect devices is connected to the interconnect bus segment with a switch, such that the interconnect device is electrically isolated from the interconnect bus segment when the switch is open. An interconnect sourcing agent connected to the interconnect bus segment controls the switches, closing the switch for one of the interconnect devices when a transaction is destined for that interconnect device, opening all of the other switches so that only one device is connected to the bus at any time.

    摘要翻译： 切换技术允许多个互连总线设备连接到单个总线段，即使互连总线协议仅允许在任何时间连接互连设备之一。 每个互连设备通过开关连接到互连总线段，使得当开关断开时，互连设备与互连总线段电隔离。 连接到互连总线段的互连采购代理控制交换机，当事务指定给该互连设备时，关闭用于互连设备之一的交换机，打开所有其他交换机，使得仅一个设备连接到总线 任何时候。

    System for requesting access to DMA channel having address not in DMA registers by replacing address of DMA register with address of requested DMA channel
    5.
    发明授权
    System for requesting access to DMA channel having address not in DMA registers by replacing address of DMA register with address of requested DMA channel 失效
    用于通过将DMA寄存器的地址替换为请求的DMA通道的地址来请求访问具有不在DMA寄存器中的地址的DMA通道的系统

    公开(公告)号：US5875351A

    公开(公告)日：1999-02-23

    申请号：US94218

    申请日：1998-06-09

    申请人： Dwight D. Riley

    发明人： Dwight D. Riley

    IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/00

    CPC分类号： G06F13/28 ,  G06F13/126

    摘要： A distributed direct memory access (DMA) architecture where greater than seven DMA channels are provided and utilized. Alternative methods are disclosed for paging or swapping DMA channels so that more than seven may exist in a computer system, but only seven may be available at a time to remain compatible with conventional DMA controller software. In one method, channels may be assigned identical addresses, with one enabled at one time. In another method, channels are assigned unique addresses but the DMA master addresses only a subset of the total number of channels so that up to seven are available to compatible software at any one time.

    摘要翻译： 分布式直接存储器访问（DMA）架构，其中提供和利用大于7个DMA通道。 公开了用于寻呼或交换DMA通道的替代方法，使得计算机系统中可能存在七个以上，但是一次只有七个可能可用于与常规DMA控制器软件保持兼容。 在一种方法中，信道可以被分配相同的地址，一次启用。 在另一种方法中，通道被分配唯一的地址，但是DMA主器件只能处理通道总数的一个子集，因此可以在任何一个时间多达七个可用于兼容的软件。

    System for DMA controller sharing control signals in conventional mode and having separate control signals for each number of channels in distributed mode
    6.
    发明授权
    System for DMA controller sharing control signals in conventional mode and having separate control signals for each number of channels in distributed mode 失效
    用于DMA控制器的系统以常规模式共享控制信号，并且在分布式模式下为每个通道数分配控制信号

    公开(公告)号：US5838993A

    公开(公告)日：1998-11-17

    申请号：US639879

    申请日：1996-04-26

    申请人： Dwight D. Riley ,  Robert C. Elliott

    发明人： Dwight D. Riley ,  Robert C. Elliott

    IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/20

    CPC分类号： G06F13/28 ,  G06F13/126

    摘要： A distributed direct memory access (DMA) architecture where DMA controllers are modified to create isolated DMA channels. Each isolated channel includes its own set of uniquely addressable registers which provide functional compatibility with conventional DMA controllers. A DMA master interacts compatibly with the computer system and transparently communicates special cycles to the isolated DMA channels to cause the distributed DMA architecture to appear as the DMA controllers. The DMA master spawns special cycles to the isolated channels for sharing common write data with multiple channels and merging read data into a single DMA controller compatible register. Channel 4 cascading is also handled via tracking registers and special cycles to maintain disable and masking functionality of channel 4 as it effects channels 0-3.

    摘要翻译： 分布式直接存储器访问（DMA）架构，其中DMA控制器被修改以创建隔离的DMA通道。 每个隔离通道都包括其自己的一组唯一可寻址寄存器，提供与常规DMA控制器的功能兼容性。 DMA主机与计算机系统兼容交互，并将特殊周期透明地传送到隔离的DMA通道，以使分布式DMA架构显示为DMA控制器。 DMA主机为隔离通道产生特殊周期，以共享具有多个通道的通用写入数据，并将读取数据合并到单个DMA控制器兼容寄存器中。 通道4级联也通过跟踪寄存器和特殊周期来处理，以保持通道4的禁用和屏蔽功能，因为它影响通道0-3。

    System for requesting access to DMA channel having address not in DMA registers by replacing address of DMA register with address of requested DMA channel
    7.
    发明授权
    System for requesting access to DMA channel having address not in DMA registers by replacing address of DMA register with address of requested DMA channel 失效
    用于通过将DMA寄存器的地址替换为请求的DMA通道的地址来请求访问具有不在DMA寄存器中的地址的DMA通道的系统

    公开(公告)号：US5765024A

    公开(公告)日：1998-06-09

    申请号：US639881

    申请日：1996-04-26

    申请人： Dwight D. Riley

    发明人： Dwight D. Riley

    IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F15/40

    CPC分类号： G06F13/28 ,  G06F13/126

    摘要： A distributed direct memory access (DMA) architecture where greater than seven DMA channels are provided and utilized. Alternative methods are disclosed for paging or swapping DMA channels so that more than seven may exist in a computer system, but only seven may be available at a time to remain compatible with conventional DMA controller software. In one method, channels may be assigned identical addresses, with one enabled at one time. In another method, channels are assigned unique addresses but the DMA master addresses only a subset of of the total number of channels so that up to seven are available to compatible software at any one time.

    摘要翻译： 分布式直接存储器访问（DMA）架构，其中提供和利用大于7个DMA通道。 公开了用于寻呼或交换DMA通道的替代方法，使得计算机系统中可能存在七个以上，但是一次只能有七个可用于与常规DMA控制器软件保持兼容。 在一种方法中，信道可以被分配相同的地址，一次启用。 在另一种方法中，通道被分配唯一的地址，但是DMA主器件只能处理通道总数的一个子集，所以在任何一个时间，多达七个可用于兼容的软件。

    Configuration and association of a supervisory virtual device function to a privileged entity
    8.
    发明授权
    Configuration and association of a supervisory virtual device function to a privileged entity 有权
    监督虚拟设备功能与特权实体的配置和关联

    公开(公告)号：US08464260B2

    公开(公告)日：2013-06-11

    申请号：US11930854

    申请日：2007-10-31

    申请人： Dwight D. Riley

    发明人： Dwight D. Riley

    IPC分类号： G06F9/48 ,  G06F9/455 ,  G06F13/20

    CPC分类号： G06F9/468 ,  G06F21/44 ,  G06F21/53 ,  G06F21/606

    摘要： A hardware device interface supporting transaction authentication is described herein. At least some illustrative embodiments include a device, including an interconnect interface, and processing logic (coupled to the bus interface) that provides access to a plurality of functions of the device through the interconnect interface. A first transaction received by the device, and associated with a function of the plurality of functions, causes a request identifier within the first transaction to be assigned to the function. Access to the function is denied if a request identifier of a second transaction, subsequent to the first transaction, does not match the request identifier assigned to the function.

    摘要翻译： 本文描述了支持事务认证的硬件设备接口。 至少一些说明性实施例包括通过互连接口提供对设备的多个功能的访问的设备，包括互连接口和处理逻辑（耦合到总线接口）。 由设备接收并与多个功能的功能相关联的第一事务使第一事务中的请求标识符被分配给该功能。 如果在第一个事务之后的第二个事务的请求标识符与分配给该函数的请求标识符不匹配，则对该函数的访问被拒绝。

    System and method for remote direct memory access over a network switch fabric
    9.
    发明授权
    System and method for remote direct memory access over a network switch fabric 有权
    通过网络交换结构进行远程直接内存访问的系统和方法

    公开(公告)号：US08374175B2

    公开(公告)日：2013-02-12

    申请号：US11116008

    申请日：2005-04-27

    申请人： Dwight D. Riley

    发明人： Dwight D. Riley

    IPC分类号： H04L12/50 ,  H04Q11/00 ,  G06F13/28

    CPC分类号： H04L45/22 ,  H04L49/3036 ,  H04L49/35 ,  H04L49/552

    摘要： A system and method for remote direct memory access over a network switch fabric. Some illustrative embodiments may include a system comprising a first system node, a direct memory access (DMA) controller, a second system node, and a network switch fabric coupling together the first and second system nodes (the network switch fabric comprises a rooted hierarchical bus). The DMA controller is configured to perform a DMA transfer of data between the first and second system nodes across the network switch fabric. The data is formatted as one or more remote DMA (RDMA) protocol messages that are routed across the network switch fabric based on a bus end-device identifier corresponding to the second system node.

    摘要翻译： 一种用于通过网络交换结构进行远程直接内存访问的系统和方法。 一些说明性实施例可以包括包括第一系统节点，直接存储器访问（DMA）控制器，第二系统节点和将第一和第二系统节点耦合在一起的网络交换结构的系统（网络交换机结构包括根分层总线 ）。 DMA控制器被配置为通过网络交换结构在第一和第二系统节点之间执行数据的DMA传输。 数据被格式化为基于与第二系统节点相对应的总线终端设备标识符通过网络交换结构路由的一个或多个远程DMA（RDMA）协议消息。

    PRESENTING MULTI-FUNCTION DEVICES BEHIND A SWITCH HIERARCHY AS A SINGLE FUNCTION DEVICE
    10.
    发明申请
    PRESENTING MULTI-FUNCTION DEVICES BEHIND A SWITCH HIERARCHY AS A SINGLE FUNCTION DEVICE 失效
    将多功能设备呈现为单功能设备的开关层级

    公开(公告)号：US20110082949A1

    公开(公告)日：2011-04-07

    申请号：US12996996

    申请日：2008-06-10

    申请人： David L. Matthews ,  Hubert E. Brinkmann ,  James Xuan Dinh ,  Dwight D. Riley ,  Paul V. Brownell

    发明人： David L. Matthews ,  Hubert E. Brinkmann ,  James Xuan Dinh ,  Dwight D. Riley ,  Paul V. Brownell

    IPC分类号： G06F3/00 ,  G06F9/00

    CPC分类号： H04L12/28 ,  G06F13/4027

    摘要： In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

    摘要翻译： 在一个实施例中，计算机系统包括至少一个主机节点，耦合到主机节点的至少一个输入/输出节点，经由交换机耦合到输入/输出节点的至少一个多功能设备，以及中间管理器 处理器包括用于阻止主机节点中用于交换机层级之后的多功能设备的枚举过程的逻辑，为与主机节点分离的管理器处理器中的多功能设备启动枚举过程，存储用于交换机的路由表 耦合到管理器处理器的存储器模块中的层次结构，并且在管理器处理器中将端点设备资源分配给主机节点。