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公开(公告)号：US09830218B2
公开(公告)日：2017-11-28
申请号：US14858448
申请日：2015-09-18
Inventor： Jin-Ho Han , Young-Su Kwon
IPC: G06F11/10 , G06F12/0895
CPC classification number: G06F11/1064 , G06F12/0895 , G06F2212/1032
Abstract: The exemplary embodiments of the invention relates to fault tolerance of a cache memory which recovers an error occurred in the cache memory or reports an error. A cache memory may include a first layer cache configured to store data requested from a processor, together with a tag related to the data and parity check bits for detecting data error and tag error; a second layer cache configured to store data requested from the first layer cache, together with parity check bits and an error correction code(ECC) bit for detecting data error and tag error; and a fault tolerance unit configured to generate an error signal indicating whether the data error or tag error occurred in at least one of the first layer cache and the second layer cache is recoverable.
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公开(公告)号：US09823963B2
公开(公告)日：2017-11-21
申请号：US15006921
申请日：2016-01-26
Inventor： Jin-Ho Han , Young-Su Kwon
IPC: G06F12/00 , G06F11/10 , G06F12/0855 , G06F12/0831 , G06F12/128 , G06F12/0811 , G06F11/14
CPC classification number: G06F11/1064 , G06F11/141 , G06F12/0804 , G06F12/0811 , G06F12/0833 , G06F12/0855 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/621
Abstract: Disclosed herein is an apparatus and method for controlling level 0 caches, capable of delivering data to a processor without errors and storing error-free data in the caches even when soft errors occur in the processor and caches. The apparatus includes: a level 0 cache #0 connected to the load/store unit of a first processor; a level 0 cache #1 connected to the load/store unit of a second processor; and a fault detection and recovery unit for reading from and writing to tag memory, data memory, and valid bit memory of the level 0 cache #0 and the level 0 cache #1, performing the write-back and flush of the level 0 cache #0 and the level 0 cache #1 based on information stored therein, and instructing the load/store units of the first and second processors to stall a pipeline and to restart an instruction #n.
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Patent Agency Ranking
3.发明授权公开(公告)号：US11842764B2
公开(公告)日：2023-12-12
申请号：US17544202
申请日：2021-12-07
Inventor： Jin-Ho Han , Byung-Jo Kim , Ju-Yeob Kim , Hye-Ji Kim , Joo-Hyun Lee , Seong-Min Kim
IPC: G11C11/4096 , G11C11/4093 , G11C11/54 , G06F7/544 , G06N3/063
CPC classification number: G11C11/4096 , G06F7/5443 , G06N3/063 , G11C11/4093 , G11C11/54
Abstract: Disclosed herein is an Artificial Intelligence (AI) processor. The AI processor includes multiple NVM AI cores for respectively performing basic unit operations required for a deep-learning operation based on data stored in NVM; SRAM for storing at least some of the results of the basic unit operations; and an AI core for performing an accumulation operation on the results of the basic unit operation.
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公开(公告)号：US09348681B2
公开(公告)日：2016-05-24
申请号：US14255481
申请日：2014-04-17
Inventor： Jin-Ho Han
CPC classification number: G06F11/0724 , G06F11/0721 , G06F11/0751
Abstract: An apparatus and method for detecting the fault of a processor are disclosed. The apparatus includes a fetch fault control unit, a decoding fault control unit, and an execution fault control unit. The fetch fault control unit detects the fault of each of fetch units of a plurality of processor cores connected to memory. The decoding fault control unit detects the fault of each of decoding units of the plurality of processor cores connected to the memory. The execution fault control unit detects the fault of each of execution units of the plurality of processor cores connected to the memory, executes the same instruction in the plurality of processor cores, determines a processor core where a fault has occurred, and provides notification of the determined processor to the fetch fault control unit and the decoding fault control unit.
Abstract translation: 公开了一种用于检测处理器故障的装置和方法。 该装置包括取出故障控制单元，解码故障控制单元和执行故障控制单元。 获取故障控制单元检测连接到存储器的多个处理器核心中的每个提取单元的故障。 解码故障控制单元检测连接到存储器的多个处理器核心中的每个解码单元的故障。 执行故障控制单元检测连接到存储器的多个处理器核心中的每个执行单元的故障，在多个处理器核心中执行相同的指令，确定出现故障的处理器核心，并且提供 确定处理器到获取故障控制单元和解码故障控制单元。
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公开(公告)号：US12231100B2
公开(公告)日：2025-02-18
申请号：US17903112
申请日：2022-09-06
Inventor： Yi-Gyeong Kim , Young-Deuk Jeon , Young-Su Kwon , Jin-Ho Han
Abstract: An apparatus for receiving a strobe signal may include an amplifier for amplifying a strobe signal input thereto, an offset generator for controlling the setting of a threshold for detecting a preamble signal by generating an offset for the amplifier, and a preamble detector for detecting a first preamble signal occurring at a point at which the amplified strobe signal is equal to or greater than the threshold and turning off the offset generator when the first preamble signal is detected.
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公开(公告)号：US11782835B2
公开(公告)日：2023-10-10
申请号：US17536573
申请日：2021-11-29
Inventor： Joo-Hyun Lee , Young-Su Kwon , Jin-Ho Han
IPC: G06F12/08 , G06F8/60 , G06F8/41 , G06F12/084
CPC classification number: G06F12/084 , G06F8/44 , G06F8/60 , G06F2212/657
Abstract: Disclosed herein is a heterogeneous system based on unified virtual memory. The heterogeneous system based on unified virtual memory may include a host for compiling a kernel program, which is source code of a user application, in a binary form and delivering the compiled kernel program to a heterogenous system architecture device, the heterogenous system architecture device for processing operation of the kernel program delivered from the host in parallel using two or more different types of processing elements, and unified virtual memory shared between the host and the heterogenous system architecture device.
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公开(公告)号：US09632894B2
公开(公告)日：2017-04-25
申请号：US14677297
申请日：2015-04-02
Inventor： Jin-Ho Han , Young-Su Kwon , Kyung-Jin Byun
CPC classification number: G06F11/2215
Abstract: The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.
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