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公开(公告)号：US20200183744A1
公开(公告)日：2020-06-11
申请号：US16583504
申请日：2019-09-26
Inventor： Young-Ho KIM , Chei-Yol KIM , Jin-Ho ON , Su-Min JANG , Gyu-Il CHA
Abstract: A worker-scheduling method in a cloud-computing system and an apparatus for the same. The worker-scheduling method includes performing a first load-distribution operation of pre-creating template workers so as to process worker execution preparation loads in a distributed manner before a worker allocation request for function execution occurs, predicting a number of workers to be pre-allocated in consideration of variation in a worker allocation request period for each function, and performing a second load distribution operation of pre-allocating ready workers by performing worker upscaling on as many template workers as the number of workers to be pre-allocated.
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公开(公告)号：US20200183746A1
公开(公告)日：2020-06-11
申请号：US16658748
申请日：2019-10-21
Inventor： Chei-Yol KIM , Young-Ho KIM , Jin-Ho ON , Su-Min JANG , Gyu-Il CHA
IPC: G06F9/50
Abstract: Disclosed herein are an apparatus and method for setting the allocation rate of a parallel-computing accelerator. The method includes monitoring the utilization rate of the parallel-computing accelerator by an application and setting a start point, at which measurement of utilization data to be used for setting the allocation rate of the parallel-computing accelerator for the application is started, using the result of monitoring the utilization rate; setting an end point, at which the measurement of the utilization data is finished, based on the monitoring result; and setting the allocation rate of the parallel-computing accelerator using the utilization data measured during a time period from the start point to the end point.
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公开(公告)号：US20180284870A1
公开(公告)日：2018-10-04
申请号：US15865158
申请日：2018-01-08
Inventor： Jin-Ho ON
IPC: G06F1/32 , G06F9/4401
Abstract: Disclosed herein are a method and apparatus for automatically determining the energy efficiency and the energy rating of a target device. An apparatus for measuring energy efficiency may automatically boot and configure a target device with regard to the energy efficiency of the target device, measure the energy efficiency of the target device, and determine the energy rating of the target device. The apparatus may provide a boot image and a workload to the target device. Also, the apparatus may control the workload that is executed in the target device. The apparatus may collect information about the execution of the workload from the target device, measure the energy efficiency of the target device using the information, and determine the energy rating of the target device.
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4.发明申请公开(公告)号：US20250061361A1
公开(公告)日：2025-02-20
申请号：US18802087
申请日：2024-08-13
Inventor： Soo-Cheol OH , Young-Chul KIM , Chei-Yol KIM , Jin-Ho ON , Sang-Min LEE , Eun-Young CHO , Ki-Sung JIN , Gyu-Il CHA
IPC: G06N10/20
Abstract: Disclosed herein is an apparatus and method for executing a magic state distillation circuit in a logical qubit quantum system. The apparatus outputs a distilled magic state |Y>L by executing a magic state |Y>L distillation circuit in which multiple multi-target CNOT operations are performed in parallel and outputs a distilled magic state |A>L by executing a magic state |A>L distillation circuit in which multiple multi-target CNOT operations are performed in parallel. The magic state |Y>L distillation circuit is configured with three code blocks, code blocks 1 and 2 being configured with multiple multi-target CNOT operations and code block 3 being configured with SL operations and measurement operations, and the magic state |A>L distillation circuit is configured with three code blocks, code blocks 1 and 2 being configured with multiple multi-target CNOT operations and code block 3 being configured with TL+ operations and measurement operations.
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公开(公告)号：US20240303523A1
公开(公告)日：2024-09-12
申请号：US18515564
申请日：2023-11-21
Inventor： Sang-Min LEE , Young-Chul KIM , Soo-Cheol OH , Jin-Ho ON , Ki-Sung JIN , Gyu-Il CHA
IPC: G06N10/40
CPC classification number: G06N10/40
Abstract: Disclosed herein are an apparatus and method for performing a fault-tolerant logical Hadamard gate operation. The apparatus is configured to perform a transversal logical Hadamard (H) operation of defining a logical quantum state and logical operators of a Hadamard-transformed logical qubit on a logical qubit of a prepared encoding flavor having an arbitrary quantum state, deform a boundary of the logical qubit while maintaining the logical quantum state using a boundary deformation technology, and perform an automatic flip of transforming a flavor of the logical qubit by flipping a rotated surface code while maintaining the logical quantum state and the definition of logical operators.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190179684A1
公开(公告)日：2019-06-13
申请号：US16213332
申请日：2018-12-07
Inventor： Jin-Ho ON , Ki-Young KIM , Gyu-Il CHA
IPC: G06F9/54
Abstract: Disclosed herein are an apparatus and method for providing long-term function execution in a serverless environment. The method for providing long-term function execution in a serverless environment is performed by an apparatus for providing long-term function execution in a serverless environment, and includes registering a long-term function execution proxy when a long-term execution request is received from a client, allocating a long-term function executor corresponding to the long-term execution request, executing, by the long-term function execution proxy, a long-term function using the allocated long-term function executor, and storing execution results of the long-term function.
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公开(公告)号：US20240127094A1
公开(公告)日：2024-04-18
申请号：US18345635
申请日：2023-06-30
Inventor： Jin-Ho ON , Chei-Yol KIM , Soo-Cheol OH , Sang-Min LEE , Gyu-Il CHA
IPC: G06N10/20
CPC classification number: G06N10/20
Abstract: Disclosed herein are a logical qubit execution apparatus and method. The logical qubit execution apparatus may be configured to execute, by a logical execution layer, a quantum circuit including requested logical qubits using a lattice surgery operation, generate, by the logical execution layer, measurement results of the logical qubits by combining measurement results of logical Pauli frames, generate, by a physical execution layer, a physical qubit circuit by converting a logical qubit operation corresponding to the measurement results of the logical qubits into a physical qubit operation, and measure, by the physical execution layer, results of an operation on physical Pauli frames by executing the physical qubit circuit.
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公开(公告)号：US20200183657A1
公开(公告)日：2020-06-11
申请号：US16575904
申请日：2019-09-19
Inventor： Jin-Ho ON , Young-Ho KIM , Chei-Yol KIM , Su-Min JANG , Gyu-Il CHA
Abstract: An apparatus and method for executing a function. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors, and the at least one program is configured to determine whether it is possible to reengineer a user function source using interface description language (IDL) code, to generate a reengineered function source by reengineering the user function source, and to execute the reengineered function source.
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公开(公告)号：US20170192450A1
公开(公告)日：2017-07-06
申请号：US15159958
申请日：2016-05-20
Inventor： Jin-Ho ON
CPC classification number: G06F1/08 , G06F1/324 , G06F1/3243 , G06F9/4825 , G06F9/505 , G06F13/24
Abstract: An apparatus and method for performing the dynamic frequency control of a central processing unit (CPU). The apparatus for performing the dynamic frequency control of a central processing unit (CPU) includes a frequency setting unit, a latency measurement unit, a frequency adjustment unit, and a control unit. The frequency setting unit sets optimum frequency using the measured amount of load. The latency measurement unit measures scheduler execution information. The frequency adjustment unit adjusts the optimum frequency using the scheduler execution information. The control unit incorporates the adjusted optimum frequency into a CPU.
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公开(公告)号：US20160342191A1
公开(公告)日：2016-11-24
申请号：US15006737
申请日：2016-01-26
Inventor： Jin-Ho ON , Sung-Ik JUN
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3228 , G06F1/329 , G06F9/5094 , Y02D10/126 , Y02D10/24
Abstract: CPU frequency scaling apparatus and method, which can select an optimal frequency based on a preset power versus efficiency table for a CPU when selecting the operating frequency based on the average load of the overall system during a specific time interval. The CPU frequency scaling apparatus includes a table generation unit for generating, for all cores, a power versus efficiency table, based on available frequencies for respective cores and power consumption values depending on loads at each frequency, an average load measurement unit for calculating an average load on all the cores, and a frequency determination unit for searching the power versus efficiency table for an optimal frequency, based on load information calculated by the average load measurement unit and current power consumption of all the cores, and determining a found optimal frequency to be a new operating frequency.
Abstract translation: CPU频率缩放装置和方法，其可以在基于在特定时间间隔期间的整个系统的平均负载选择操作频率时基于CPU的预设功率对效率表来选择最佳频率。 CPU频率缩放装置包括表生成单元，用于根据各个频率的负载，根据各个核的可用频率和功率消耗值，针对所有的核产生功率对效率表，计算平均负载测量单元 根据平均负载测量单元计算的负载信息和所有核心的当前功耗，将用于搜索功率对效率表的功率对效率表进行搜索以获得最佳频率的频率确定单元，并将找到的最佳频率确定为 成为新的运行频率。
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