公开(公告)号：US10937883B2

公开(公告)日：2021-03-02

申请号：US16662907

申请日：2019-10-24

申请人： ELPIS TECHNOLOGIES INC.

发明人： Choonghyun Lee ,  Takashi Ando ,  Jingyun Zhang ,  Pouya Hashemi ,  Alexander Reznicek

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/417

摘要： Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.

公开(公告)号：US11063129B2

公开(公告)日：2021-07-13

申请号：US16521777

申请日：2019-07-25

申请人： ELPIS TECHNOLOGIES INC.

发明人： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Peng Xu

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L21/762 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/10

摘要： Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes laterally forming a spacer on a side of the semiconductor structure. The method further includes performing a thermal anneal on the semiconductor structure. The method further includes performing an etch to remove materials formed by the thermal anneal.

公开(公告)号：US10832955B2

公开(公告)日：2020-11-10

申请号：US16392064

申请日：2019-04-23

申请人： ELPIS TECHNOLOGIES INC.

发明人： Peng Xu ,  Kangguo Cheng ,  Yann Mignot ,  Choonghyun Lee

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3213 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/417 ,  H01L21/311 ,  H01L29/775

摘要： A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.