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公开(公告)号：US10937883B2
公开(公告)日：2021-03-02
申请号：US16662907
申请日：2019-10-24
IPC分类号： H01L29/49 , H01L29/78 , H01L29/08 , H01L27/092 , H01L21/8238 , H01L21/28 , H01L21/3215 , H01L23/535 , H01L29/66 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L27/088 , H01L29/417
摘要： Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.
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公开(公告)号：US10727139B2
公开(公告)日：2020-07-28
申请号：US16240146
申请日：2019-01-04
发明人： Terry Hook , Ardasheir Rahman , Joshua Rubin , Chen Zhang
IPC分类号： H01L21/84 , H01L27/12 , H01L23/00 , H01L23/528 , H01L21/768 , H01L23/522 , H01L27/06 , H01L21/8234 , H01L21/822 , H01L27/088
摘要： Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.
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公开(公告)号：US10727121B2
公开(公告)日：2020-07-28
申请号：US16201448
申请日：2018-11-27
发明人： Robert L. Bruce , Cyril Cabral, Jr. , Gregory M. Fritz , Eric A. Joseph , Michael F. Lofaro , Hiroyuki Miyazoe , Kenneth P. Rodbell , Ghavam Shahidi
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.
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公开(公告)号：US10714341B2
公开(公告)日：2020-07-14
申请号：US15591584
申请日：2017-05-10
IPC分类号： H01L21/02 , H01L21/027 , G03F7/20 , H01L21/768 , H01L21/311 , H01L21/033 , H01L23/528
摘要： Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.
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公开(公告)号：US11063129B2
公开(公告)日：2021-07-13
申请号：US16521777
申请日：2019-07-25
发明人： Kangguo Cheng , Choonghyun Lee , Juntao Li , Peng Xu
IPC分类号： H01L29/417 , H01L29/66 , H01L21/762 , H01L21/324 , H01L21/8234 , H01L29/78 , H01L29/10
摘要： Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes laterally forming a spacer on a side of the semiconductor structure. The method further includes performing a thermal anneal on the semiconductor structure. The method further includes performing an etch to remove materials formed by the thermal anneal.
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公开(公告)号：US10978576B2
公开(公告)日：2021-04-13
申请号：US16597713
申请日：2019-10-09
发明人： Chi-Chun Liu , Chun Wing Yeung , Robin Hsin Kuo Chao , Zhenxing Bi , Kristin Schmidt , Yann Mignot
IPC分类号： H01L29/66 , H01L21/311 , H01L29/40 , H01L29/423 , H01L21/3105 , H01L29/78
摘要： Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided.
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公开(公告)号：US10966351B2
公开(公告)日：2021-03-30
申请号：US16681958
申请日：2019-11-13
发明人： Xiaojin Wei , Allan C. VanDeventer
IPC分类号： H05K7/20 , H01L23/427 , H01L23/367 , H01L21/48
摘要： The present invention provides a heat dissipation device including a baseplate, one or more heat pipes in thermal communication with the baseplate, where the one or more heat pipes has one or more internal cavities, one or more vapor chambers coupled to the one or more heat pipes, where the one or more vapor chambers has one or more internal cavities, where the one or more internal cavities of the one or more heat pipes and the one or more internal cavities of the one or more the vapor chambers are contiguous, where the one or more vapor chambers extends from the one or more heat pipes, and heat conducting fins coupled to the one or more vapor chambers, where the one or more heat conducting fins extends from the one or more vapor chambers.
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公开(公告)号：US10804166B2
公开(公告)日：2020-10-13
申请号：US16598517
申请日：2019-10-10
IPC分类号： H01L21/84 , H01L27/12 , H01L27/092 , H01L21/8238 , H01L29/161 , H01L21/02 , H01L21/306 , H01L29/167 , H01L21/326 , H01L21/265 , H01L21/762 , H01L29/06 , H01L29/78
摘要： A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
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公开(公告)号：US10978454B2
公开(公告)日：2021-04-13
申请号：US16776686
申请日：2020-01-30
IPC分类号： H01L21/00 , H01L27/092 , H01L29/78 , H01L27/088 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L29/423 , H01L29/786 , H01L25/07
摘要： A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.
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公开(公告)号：US10957536B2
公开(公告)日：2021-03-23
申请号：US16671686
申请日：2019-11-01
IPC分类号： H01L21/033 , H01L21/311 , H01L21/027 , H01L21/3105 , H01L21/8238
摘要： A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.
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