公开(公告)号：US20050276120A1

公开(公告)日：2005-12-15

申请号：US10864947

申请日：2004-06-10

申请人： Ed Hsia ,  Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike

发明人： Ed Hsia ,  Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3413 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409

摘要： Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.

摘要翻译： 提供了将具有三个或多个数据状态的多级闪存单元（MLB）的扇区擦除为单个数据状态的方法。 本发明采用交互式扇区擦除算法，其在两个或多个擦除阶段中重复地擦除，验证，软程序和对扇区进行编程，以实现高度紧凑的数据状态分布。 在一个示例中，该算法基本上将第一阶段中使用交互式擦除，软编程和编程脉冲的扇区的所有MLB单元擦除到中间状态和对应的阈值电压值。 然后在第二阶段中，该算法使用额外的交互擦除和软编程脉冲进一步擦除扇区的所有MLB单元，直到达到对应于单元的期望的最终阈值电压值的最终数据状态。 可选地，该算法可以包括一个或多个类似操作的附加阶段，其连续地将该扇区的存储器单元带到压缩的公共擦除状态，以备后续的编程操作。 在该方法的一个方面中，为这些阶段选择的实际阈值和/或数据状态可以是预定的，并且由用户输入到存储器设备。

公开(公告)号：US07251158B2

公开(公告)日：2007-07-31

申请号：US10864947

申请日：2004-06-10

申请人： Ed Hsia ,  Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike

发明人： Ed Hsia ,  Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike

IPC分类号： G11C11/34

CPC分类号： G11C16/3413 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409

摘要： Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.

摘要翻译： 提供了将具有三个或多个数据状态的多级闪存单元（MLB）的扇区擦除为单个数据状态的方法。 本发明采用交互式扇区擦除算法，其在两个或多个擦除阶段中重复地擦除，验证，软程序和对扇区进行编程，以实现高度紧凑的数据状态分布。 在一个示例中，该算法基本上将第一阶段中使用交互式擦除，软编程和编程脉冲的扇区的所有MLB单元擦除到中间状态和对应的阈值电压值。 然后在第二阶段中，该算法使用额外的交互擦除和软编程脉冲进一步擦除扇区的所有MLB单元，直到达到与单元的期望的最终阈值电压值对应的最终数据状态。 可选地，该算法可以包括一个或多个类似操作的附加阶段，其连续地将该扇区的存储器单元带到压缩的公共擦除状态，以备后续的编程操作。 在该方法的一个方面中，为这些阶段选择的实际阈值和/或数据状态可以是预定的，并且由用户输入到存储器设备。

公开(公告)号：US20060152974A1

公开(公告)日：2006-07-13

申请号：US11034642

申请日：2005-01-13

申请人： Fatima Bathul ,  Darlene Hamilton ,  Masato Horiike

发明人： Fatima Bathul ,  Darlene Hamilton ,  Masato Horiike

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5671

摘要： Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough. Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

公开(公告)号：US07130210B2

公开(公告)日：2006-10-31

申请号：US11034642

申请日：2005-01-13

申请人： Fatima Bathul ,  Darlene Hamilton ,  Masato Horiike

发明人： Fatima Bathul ,  Darlene Hamilton ,  Masato Horiike

IPC分类号： G11C17/00

CPC分类号： G11C16/16 ,  G11C11/5671

摘要： Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

公开(公告)号：US07038948B2

公开(公告)日：2006-05-02

申请号：US10946809

申请日：2004-09-22

申请人： Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike ,  Eugen Gershon ,  Michael Van Buskirk

发明人： Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike ,  Eugen Gershon ,  Michael Van Buskirk

IPC分类号： G11C16/04

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/34 ,  G11C16/3418 ,  G11C2211/5634

摘要： The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.

摘要翻译： 本发明涉及用于确定双面ONO闪速存储器单元中的位的电平的技术，其中双面ONO闪存单元的每个位可以被编程为多个电平。 本发明的一个或多个方面考虑到一位上的电荷电平对另一位可能具有的影响，或称为互补位干扰的影响。 被称为跨导的度量被用于使位电平确定提供更大程度的分辨率和精度。 以这种方式，根据本发明的一个或多个方面确定比特级别减轻了错误或错误的读取。

公开(公告)号：US20060062054A1

公开(公告)日：2006-03-23

申请号：US10946809

申请日：2004-09-22

申请人： Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike ,  Eugen Gershon ,  Michael Buskirk

发明人： Darlene Hamilton ,  Fatima Bathul ,  Masato Horiike ,  Eugen Gershon ,  Michael Buskirk

IPC分类号： G11C7/06 ,  G11C11/34

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/34 ,  G11C16/3418 ,  G11C2211/5634

摘要： The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.

摘要翻译： 本发明涉及用于确定双面ONO闪速存储器单元中的位的电平的技术，其中双面ONO闪存单元的每个位可以被编程为多个电平。 本发明的一个或多个方面考虑到一位上的电荷电平对另一位可能具有的影响，或称为互补位干扰的影响。 被称为跨导的度量被用于使位电平确定提供更大程度的分辨率和精度。 以这种方式，根据本发明的一个或多个方面确定比特级别减轻了错误或错误的读取。

公开(公告)号：US20090103357A1

公开(公告)日：2009-04-23

申请号：US11874076

申请日：2007-10-17

申请人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

发明人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C2211/5621

摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.

摘要翻译： 提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。 交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。 在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。 选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。 学习元件对被编程以确定每个程序级的学习程序漏极电压。 这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

公开(公告)号：US07692962B2

公开(公告)日：2010-04-06

申请号：US11958557

申请日：2007-12-18

申请人： Darlene Hamilton ,  Fatima Bathul ,  Ken Tanpairoj ,  Ou Li ,  David Rogers ,  Roger Tsao

发明人： Darlene Hamilton ,  Fatima Bathul ,  Ken Tanpairoj ,  Ou Li ,  David Rogers ,  Roger Tsao

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5628 ,  Y10T29/49002

摘要： A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.

摘要翻译： 提供了一种简化状态存储器件以及形成和编程器件的多级闪存单元元件对的方法，每个元件被配置为存储空白电平或两个或更多个程序电平。 在一个实施例中，缩减状态存储器件包括被配置为在存储器单元元件对中存储包括两个空白电平，两个程序电平以及一个空白电平和一个程序电平的多个程序模式组合的一个模式组合的组件， 电平差别小于预定值。 在一个实施例中，形成存储器件的方法包括形成多级闪速存储器阵列的至少一个存储器件，每个存储器单元包括两个或多个存储器元件，每个存储器元件被配置为存储三个或更多个电平，并且排除 可存储在至少一个存储单元中的一个或多个程序模式组合。

公开(公告)号：US07656705B2

公开(公告)日：2010-02-02

申请号：US11874076

申请日：2007-10-17

申请人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

发明人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C2211/5621

摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.

摘要翻译： 提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。 交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。 在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。 选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。 学习元件对被编程以确定每个程序级的学习程序漏极电压。 这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

公开(公告)号：US20090154235A1

公开(公告)日：2009-06-18

申请号：US11958557

申请日：2007-12-18

申请人： Darlene Hamilton ,  Fatima Bathul ,  Ken Tanpairoj ,  Ou Li ,  David Rogers ,  Roger Tsao

发明人： Darlene Hamilton ,  Fatima Bathul ,  Ken Tanpairoj ,  Ou Li ,  David Rogers ,  Roger Tsao

IPC分类号： G11C16/04 ,  H01S4/00

CPC分类号： G11C16/0475 ,  G11C11/5628 ,  Y10T29/49002

摘要： A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.

摘要翻译： 提供了一种简化状态存储器件以及形成和编程器件的多级闪存单元元件对的方法，每个元件被配置为存储空白电平或两个或更多个程序电平。 在一个实施例中，缩减状态存储器件包括被配置为在存储器单元元件对中存储包括两个空白电平，两个程序电平以及一个空白电平和一个程序电平的多个程序模式组合的一个模式组合的组件， 电平差别小于预定值。 在一个实施例中，形成存储器件的方法包括形成多级闪速存储器阵列的至少一个存储器件，每个存储器单元包括两个或多个存储器元件，每个存储器元件被配置为存储三个或更多个电平，并且排除 可存储在至少一个存储单元中的一个或多个程序模式组合。