公开(公告)号：US20110153999A1

公开(公告)日：2011-06-23

申请号：US12644151

申请日：2009-12-22

申请人： Edson Borin ,  Youfeng Wu

发明人： Edson Borin ,  Youfeng Wu

IPC分类号： G06F9/312

CPC分类号： G06F9/30145 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

摘要翻译： 公开了用于管理部分提交检查点的示例性方法和装置。 所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于 与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

公开(公告)号：US20100083236A1

公开(公告)日：2010-04-01

申请号：US12242371

申请日：2008-09-30

申请人： Joao Paulo Porto ,  Edson Borin ,  Youfeng Wu ,  Cheng Wang

发明人： Joao Paulo Porto ,  Edson Borin ,  Youfeng Wu ,  Cheng Wang

IPC分类号： G06F9/44

CPC分类号： G06F9/45516

摘要： Methods and apparatus relating to compact trace trees for dynamic binary parallelization are described. In one embodiment, a compact trace tree (CTT) is generated to improve the effectiveness of dynamic binary parallelization. CTT may be used to determine which traces are to be duplicated and specialized for execution on separate processing elements. Other embodiments are also described and claimed.

摘要翻译： 描述了用于动态二进制并行化的紧凑跟踪树的方法和设备。 在一个实施例中，生成紧凑跟踪树（CTT）以提高动态二进制并行化的有效性。 可以使用CTT来确定哪些跟踪被复制并专用于在单独的处理元件上执行。 还描述和要求保护其他实施例。

公开(公告)号：US08332558B2

公开(公告)日：2012-12-11

申请号：US12242371

申请日：2008-09-30

申请人： Joao Paulo Porto ,  Edson Borin ,  Youfeng Wu ,  Cheng Wang

发明人： Joao Paulo Porto ,  Edson Borin ,  Youfeng Wu ,  Cheng Wang

IPC分类号： G06F9/44 ,  G06F9/00

CPC分类号： G06F9/45516

摘要： Methods and apparatus relating to compact trace trees for dynamic binary parallelization are described. In one embodiment, a compact trace tree (CTT) is generated to improve the effectiveness of dynamic binary parallelization. CTT may be used to determine which traces are to be duplicated and specialized for execution on separate processing elements. Other embodiments are also described and claimed.

摘要翻译： 描述了用于动态二进制并行化的紧凑跟踪树的方法和设备。 在一个实施例中，生成紧凑跟踪树（CTT）以提高动态二进制并行化的有效性。 可以使用CTT来确定哪些跟踪被复制并专用于在单独的处理元件上执行。 还描述和要求保护其他实施例。

公开(公告)号：US20160116965A1

公开(公告)日：2016-04-28

申请号：US14986678

申请日：2016-01-02

申请人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

发明人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC分类号： G06F1/32 ,  G06F9/50

CPC分类号： G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US08549267B2

公开(公告)日：2013-10-01

申请号：US12644151

申请日：2009-12-22

申请人： Edson Borin ,  Youfeng Wu

发明人： Edson Borin ,  Youfeng Wu

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30145 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

摘要翻译： 公开了用于管理部分提交检查点的示例性方法和装置。 所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于 与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

公开(公告)号：US08443353B2

公开(公告)日：2013-05-14

申请号：US12890639

申请日：2010-09-25

申请人： Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

发明人： Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC分类号： G06F9/45

摘要： An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：US07506217B2

公开(公告)日：2009-03-17

申请号：US11325773

申请日：2005-12-30

申请人： Edson Borin ,  Cheng C. Wang ,  Youfeng Wu

发明人： Edson Borin ,  Cheng C. Wang ,  Youfeng Wu

IPC分类号： G06F11/00

CPC分类号： G06F11/1004

摘要： A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of the basic block. In addition, the basic block is instrumented to verify that contents of the signature register match a basic block signature at a beginning of the basic block. In one embodiment, an instruction is inserted within the basic block to cause the signature register to store a predetermined value if the contents of the signature register match a basic block signature. In one embodiment, a basic block may be subdivided into a plurality of regions; each region is assigned a signature and instrumented to update the signature register at a beginning of each region. Other embodiments are described and claimed.

摘要翻译： 一种用于软错误检测的基于软件的控制流程检查的方法和装置。 在一个实施例中，该方法包括在基本块的结尾处对目标程序的一个基本块的仪表进行更新具有后继基本块签名的签名寄存器。 另外，基本块被验证以验证签名寄存器的内容是否与基本块开头的基本块签名相匹配。 在一个实施例中，如果签名寄存器的内容与基本块签名匹配，则在基本块内插入指令以使签名寄存器存储预定值。 在一个实施例中，基本块可以被细分为多个区域; 每个区域都被分配一个签名，并在每个区域的开头进行检测以更新签名寄存器。 描述和要求保护其他实施例。

公开(公告)号：US20160116964A1

公开(公告)日：2016-04-28

申请号：US14986677

申请日：2016-01-02

申请人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

发明人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC分类号： G06F1/32 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38

CPC分类号： G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US20160116963A1

公开(公告)日：2016-04-28

申请号：US14986676

申请日：2016-01-02

申请人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

发明人： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC分类号： G06F1/32 ,  G06F9/50

摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

摘要翻译： 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

公开(公告)号：US20140032885A1

公开(公告)日：2014-01-30

申请号：US14041170

申请日：2013-09-30

申请人： Edson Borin ,  Youfeng Wu

发明人： Edson Borin ,  Youfeng Wu

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

摘要翻译： 公开了用于管理部分提交检查点的示例性方法和装置。 所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于 与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。