公开(公告)号：US11637192B2

公开(公告)日：2023-04-25

申请号：US17355977

申请日：2021-06-23

申请人： Electronics and Telecommunications Research Institute

发明人： Kun Sik Park ,  Jong Il Won ,  Doo Hyung Cho ,  Hyun Gyu Jang ,  Dong Yun Jung

IPC分类号： H01L29/749 ,  H01L29/745 ,  H01L29/66

摘要： The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.

公开(公告)号：US11784247B2

公开(公告)日：2023-10-10

申请号：US17792070

申请日：2021-06-10

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Kun Sik Park ,  Jong Il Won ,  Doo Hyung Cho ,  Dong Yun Jung ,  Hyun Gyu Jang

IPC分类号： H01L29/745 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/7455 ,  H01L29/0839 ,  H01L29/1012 ,  H01L29/66378

摘要： A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.