公开(公告)号：US20140091388A1

公开(公告)日：2014-04-03

申请号：US14100780

申请日：2013-12-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Gi KIM ,  Jin-Gun KOO ,  Seong Wook YOO ,  Jong-Moon PARK ,  Jin Ho LEE ,  KYOUNG IL NA ,  Yil Suk Yang ,  Jongdae KIM

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。

公开(公告)号：US20140077302A1

公开(公告)日：2014-03-20

申请号：US13846701

申请日：2013-03-18

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kunsik PARK ,  KYOUNG IL NA ,  Jin Ho LEE ,  JIN-GUN KOO

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/6609 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/861

Abstract: According to a power rectifying device of embodiments of the inventive concept, a gate electrode, a source region, and a body region are connected in common to a first terminal, and a substrate beside the body region is connected to a second terminal. Thus, the power rectifying device having two terminals is realized. The gate electrode has s spacer-shape. Thus, a width of the gate electrode may be controlled to accurately control a channel length of a channel region of a transistor structure in the power rectifying device.

Abstract translation: 根据本发明构思的实施例的功率整流装置，栅电极，源极区和体区共同连接到第一端子，并且身体区域旁边的衬底连接到第二端子。 因此，实现具有两个端子的动力整流装置。 栅电极具有间隔物形状。 因此，可以控制栅电极的宽度以精确地控制功率整流装置中的晶体管结构的沟道区的沟道长度。

公开(公告)号：US20130309824A1

公开(公告)日：2013-11-21

申请号：US13723674

申请日：2012-12-21

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： KYOUNG IL NA

IPC: H01L29/66

CPC classification number: H01L29/66825 ,  H01L21/2254 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

Abstract: Provided is a method of manufacturing a semiconductor device. The method may include etching a first conductive type semiconductor substrate to form a first trench, forming a second trench extending from the first trench, diffusing impurities into inner walls of the second trench to form a second conductive type impurity region surrounding the second trench, forming a floating dielectric layer covering inner walls of the second trench and a floating electrode filling the second trench, and forming a gate dielectric layer covering inner walls of the first trench and a gate electrode filling the first trench.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括蚀刻第一导电类型半导体衬底以形成第一沟槽，形成从第一沟槽延伸的第二沟槽，将杂质扩散到第二沟槽的内壁，以形成环绕第二沟槽的第二导电型杂质区，形成 覆盖所述第二沟槽的内壁的浮动介电层和填充所述第二沟槽的浮置电极，以及形成覆盖所述第一沟槽的内壁和填充所述第一沟槽的栅电极的栅介质层。