公开(公告)号：US08878070B2

公开(公告)日：2014-11-04

申请号：US13222542

申请日：2011-08-31

申请人： Emi Kashiwaya ,  Osamu Kindo ,  Noriou Shimada

发明人： Emi Kashiwaya ,  Osamu Kindo ,  Noriou Shimada

IPC分类号： H05K1/00 ,  H01L23/31 ,  H01L21/56 ,  H05K3/00 ,  H05K3/28 ,  H01L23/00 ,  H05K1/02 ,  H05K3/40 ,  H01L23/498

CPC分类号： H05K3/284 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3142 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/58 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/0097 ,  H05K3/4015 ,  H05K2203/041 ,  H05K2203/1316 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wiring board of this invention includes a product formation area in which are arranged a plurality of product formation sections on which a semiconductor chip is mounted; a molding area that is provided on an outer circumferential side of the product formation area, and with which a seal portion that covers the semiconductor chips mounted on the product formation sections makes contact; a clamp area that is provided on an outer circumferential side of the molding area, and that is held by a molding die that forms the seal portion; wiring that is provided in the product formation area, and that is electrically connected to the semiconductor chips; a first solid pattern that is provided in the molding area, and in which a plurality of dots are arranged; and a second solid pattern that is provided in the clamp area, and in which a plurality of dots that are larger than the dots of the first solid pattern are arranged.

摘要翻译： 本发明的布线基板包括产品形成区域，在该产品形成区域中布置有安装有半导体芯片的多个产品形成部分; 成形区域，其设置在所述产品形成区域的外周侧，并且覆盖安装在所述产品形成部分上的所述半导体芯片的密封部分与所述成型区域接触; 夹紧区域，设置在成型区域的外周侧，并且由形成密封部的成型模具保持; 设置在产品形成区域中并与半导体芯片电连接的布线; 第一固体图案，其设置在成型区域中，并且其中布置有多个点; 以及设置在所述夹持区域中的第二固体图案，并且其中布置有大于所述第一固体图案的点的多个点。

公开(公告)号：US07759808B2

公开(公告)日：2010-07-20

申请号：US12285831

申请日：2008-10-15

申请人： Osamu Kindo

发明人： Osamu Kindo

IPC分类号： H01L23/544 ,  H01L21/76 ,  H01L21/00

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68331 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10S438/975 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second recognition mark which is formed into a smaller shape than the first recognition mark so that the position of the dividing line can be microscopically detected by using a recognition camera. The second recognition mark is arranged so that its center line is positioned on a line that extends from a dicing line, and has a pattern shape which is formed so as to be linearly symmetric with respect to the center line. This pattern shape is formed so that the ratio of a length occupying a direction parallel to the dicing line is larger than that occupying a direction perpendicular to the dicing line, and includes a flow region for promoting the flow of an etchant for forming the pattern shape.

摘要翻译： 本发明包括第一识别标记，该第一识别标记被布置在具有实现的多个半导体芯片的实施区域的周边的框架部分中，使得可以通过使用识别照相机宏观地检测半导体衬底的位置，并且 第二识别标记形成为比第一识别标记更小的形状，使得可以通过使用识别照相机来显微检测分割线的位置。 第二识别标记被布置成使得其中心线位于从切割线延伸的线上，并且具有形成为相对于中心线线性对称的图案形状。 这种图案形状形成为使得占据与切割线平行的方向的长度的比例大于垂直于切割线的方向的比例，并且包括用于促进用于形成图案形状的蚀刻剂的流动的流动区域 。

公开(公告)号：US20090102071A1

公开(公告)日：2009-04-23

申请号：US12285831

申请日：2008-10-15

申请人： Osamu Kindo

发明人： Osamu Kindo

IPC分类号： H01L23/544 ,  H01L21/302

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68331 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10S438/975 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second recognition mark which is formed into a smaller shape than the first recognition mark so that the position of the dividing line can be microscopically detected by using a recognition camera. The second recognition mark is arranged so that its center line is positioned on a line that extends from a dicing line, and has a pattern shape which is formed so as to be linearly symmetric with respect to the center line. This pattern shape is formed so that the ratio of a length occupying a direction parallel to the dicing line is larger than that occupying a direction perpendicular to the dicing line, and includes a flow region for promoting the flow of an etchant for forming the pattern shape.

摘要翻译： 本发明包括第一识别标记，该第一识别标记被布置在具有实现的多个半导体芯片的实施区域的周边的框架部分中，使得可以通过使用识别照相机宏观地检测半导体衬底的位置，并且 第二识别标记形成为比第一识别标记更小的形状，使得可以通过使用识别照相机来显微检测分割线的位置。 第二识别标记被布置成使得其中心线位于从切割线延伸的线上，并且具有形成为相对于中心线线性对称的图案形状。 这种图案形状形成为使得占据与切割线平行的方向的长度的比例大于垂直于切割线的方向的比例，并且包括用于促进用于形成图案形状的蚀刻剂的流动的流动区域 。