公开(公告)号：US20110147849A1

公开(公告)日：2011-06-23

申请号：US12868488

申请日：2010-08-25

申请人： Emmanuel AUGENDRE ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

发明人： Emmanuel AUGENDRE ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

IPC分类号： H01L27/088 ,  H01L21/98

CPC分类号： H01L27/1104 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11

摘要： An integrated circuit including: a first transistor; a second transistor, arranged on the first transistor, whereof a channel region is formed in a semiconductor layer including two approximately parallel primary faces; a portion of an electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged between the portion of the electrically conductive material and the channel region of the second transistor; and in which the section of the channel region of the second transistor is included in the section of the portion of the electrically conductive material, and the channel region of the second transistor is arranged between the portion of the electrically conductive material and a gate of the second transistor.

摘要翻译： 一种集成电路，包括：第一晶体管; 第二晶体管，布置在第一晶体管上，沟道区形成在包括两个近似平行的主面的半导体层中; 导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且其中第二晶体管的沟道区域的部分包括在导电材料部分的部分中，并且第二晶体管的沟道区域被布置在导电材料的部分和栅极之间 第二晶体管。

公开(公告)号：US08853785B2

公开(公告)日：2014-10-07

申请号：US12868488

申请日：2010-08-25

申请人： Emmanuel Augendre ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

发明人： Emmanuel Augendre ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

IPC分类号： H01L27/088

CPC分类号： H01L27/1104 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11

摘要： An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.

摘要翻译： 一种集成电路，至少包括：第一MOS晶体管; 配置在所述第一MOS晶体管上的第二MOS晶体管，所述第二MOS晶体管在至少一个包含两个近似平行的主面的半导体层中包括沟道区; 至少一个导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 至少布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且在与半导体层的两个主面平行的平面中的第二晶体管的沟道区域的一部分被包括在投影在所述平面中的导电材料部分的一部分中。

公开(公告)号：US08183630B2

公开(公告)日：2012-05-22

申请号：US12474851

申请日：2009-05-29

申请人： Perrine Batude ,  Laurent Clavelier ,  Marie-Anne Jaud ,  Olivier Thomas ,  Maud Vinet

发明人： Perrine Batude ,  Laurent Clavelier ,  Marie-Anne Jaud ,  Olivier Thomas ,  Maud Vinet

IPC分类号： H01L29/66 ,  H01L29/94

CPC分类号： H01L27/1104 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

摘要： A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.

摘要翻译： 一种微电子器件，包括：由一叠层叠层的衬底，位于所述堆叠的给定电平处的至少一个第一晶体管，位于所述叠层的第二电平以上的至少一个第二晶体管，高于所述给定电平，所述第一晶体管 包括与第二晶体管的沟道区相对的栅电极，第一晶体管和第二晶体管被绝缘区隔开，所述绝缘区由几种不同的介电材料构成，包括第一电介质材料和第二电介质材料。

公开(公告)号：US20090294822A1

公开(公告)日：2009-12-03

申请号：US12474851

申请日：2009-05-29

申请人： Perrine Batude ,  Laurent Clavelier ,  Marie-Anne Jaud ,  Olivier Thomas ,  Maud Vinet

发明人： Perrine Batude ,  Laurent Clavelier ,  Marie-Anne Jaud ,  Olivier Thomas ,  Maud Vinet

IPC分类号： H01L27/088

CPC分类号： H01L27/1104 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203

摘要： A microelectronic device comprising: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by means of an insulating zone, said insulating zone having, in a first region between said gate of said first transistor and said channel of said second transistor, a composition and thickness provided so as to enable a coupling between the gate electrode of the first transistor and the channel of the second transistor, said insulating zone comprising a second region around the first region, between the access zones of the first and the second transistor of thickness and composition different to those of said first region.

摘要翻译： 一种微电子器件，包括：由一叠层叠层的衬底，位于所述堆叠的给定电平的至少一个第一晶体管，位于所述叠层的第二电平以上的至少一个第二晶体管，高于所述给定电平，所述第一晶体管 包括与所述第二晶体管的沟道区相对的栅电极，所述第一晶体管和所述第二晶体管通过绝缘区隔开，所述绝缘区在所述第一晶体管的所述栅极和所述第一晶体管的所述沟道之间的第一区域中 所述第二晶体管的组成和厚度设置成使得能够在所述第一晶体管的栅电极和所述第二晶体管的沟道之间的耦合，所述绝缘区包括所述第一区周围的第二区， 以及第二晶体管的厚度和组成不同于所述第一区域的晶体管。

公开(公告)号：US07678635B2

公开(公告)日：2010-03-16

申请号：US12030672

申请日：2008-02-13

申请人： Laurent Clavelier ,  Frederic Mayer ,  Maud Vinet ,  Simon Deleonibus

发明人： Laurent Clavelier ,  Frederic Mayer ,  Maud Vinet ,  Simon Deleonibus

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/28123 ,  H01L29/66325 ,  H01L29/66659 ,  H01L29/7391 ,  H01L29/78

摘要： Method of producing a transistor, comprising in particular the steps of: producing a first etching mask on a gate layer, one edge of the first mask forming a pattern of the first edge of a gate of the transistor, etching the gate layer according to the first etching mask, first ion implantation in a part of the substrate not covered by the gate layer, trimming the first etching mask over a length equal to a gate length of the transistor, producing a second etching mask on the gate layer, removing the first etching mask etching the gate layer according to the second etching mask, second ion implantation in another part of the substrate.

摘要翻译： 制造晶体管的方法，其特别包括以下步骤：在栅极层上制造第一蚀刻掩模，第一掩模的一个边缘形成晶体管的栅极的第一边缘的图案，根据该栅极层蚀刻栅极层 第一蚀刻掩模，在未被栅极层覆盖的衬底的一部分中的第一离子注入，在等于晶体管的栅极长度的长度上修整第一蚀刻掩模，在栅极层上产生第二蚀刻掩模，去除第一蚀刻掩模 蚀刻掩模根据第二蚀刻掩模蚀刻栅极层，在衬底的另一部分中进行第二离子注入。

公开(公告)号：US08809964B2

公开(公告)日：2014-08-19

申请号：US12865549

申请日：2009-02-11

申请人： François Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

发明人： François Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L29/42348 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/792

摘要： An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

摘要翻译： 一种用于生产电子组件的电子组件和相关方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，并且其中在预定的第一深度形成第一捕集区。 第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。 来自第一晶体管的有用信息包括该晶体管内的电荷传输。 可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。

公开(公告)号：US20110001184A1

公开(公告)日：2011-01-06

申请号：US12865549

申请日：2009-02-11

申请人： Francois Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

发明人： Francois Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42348 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/792

摘要： An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

摘要翻译： 一种用于生产电子组件的电子组件和相关联的方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，其中在预定的第一深度处形成第一捕集区。 第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。 来自第一晶体管的有用信息包括该晶体管内的电荷传输。 可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。

公开(公告)号：US07989327B2

公开(公告)日：2011-08-02

申请号：US12340839

申请日：2008-12-22

申请人： Benjamin Vincent ,  Laurent Clavelier ,  Jean-Francois Damlencourt

发明人： Benjamin Vincent ,  Laurent Clavelier ,  Jean-Francois Damlencourt

IPC分类号： H01L21/20

CPC分类号： H01L21/32105 ,  H01L21/7624

摘要： A method of manufacturing a semi-conductor on insulator substrate from an SOI substrate, wherein a Si1-xGex layer is formed on a superficial layer of silicon having a buried electrical insulating layer. A silicon oxide layer is formed on the Si1-xGex layer. The resulting stack of silicon, Si1-xGex and silicon oxide layers is etched up to the buried insulating layer leaving an island of the stack, or up to the superficial layer leaving a zone of silicon and an island of the stack. A mask is formed to protect against oxidation on the etched structure, wherein the protective mask only leaves visible the silicon oxide layer of the island. The germanium of the Si1-xGex layer is condensed on the island to obtain an island comprising a layer that is enriched in germanium, or even a layer of germanium, on the insulating layer, with a silicon oxide layer on top of it.

摘要翻译： 一种从SOI衬底制造绝缘体上半导体衬底的方法，其中在具有掩埋电绝缘层的硅的表面层上形成Si1-xGex层。 在Si1-xGex层上形成氧化硅层。 所得到的硅叠层Si1-xGex和氧化硅层被蚀刻到掩埋绝缘层上，留下堆叠的岛，或直到离开硅区域和堆叠岛的表层。 形成掩模以防止在蚀刻结构上的氧化，其中保护掩模仅使岛的氧化硅层可见。 Si1-xGex层的锗在岛上被冷凝，以获得在绝缘层上富含锗或甚至一层锗的层，其上面具有氧化硅层。

公开(公告)号：US20100221891A1

公开(公告)日：2010-09-02

申请号：US12705039

申请日：2010-02-12

申请人： FRANCK FOURNEL ,  Thomas Signamarcheix ,  Laurent Clavelier ,  Chrystel Deguet

发明人： FRANCK FOURNEL ,  Thomas Signamarcheix ,  Laurent Clavelier ,  Chrystel Deguet

IPC分类号： H01L21/30

CPC分类号： H01L21/76254

摘要： A method of producing a hybrid substrate includes preparing a monocrystalline first substrate to obtain two surface portions. A temporary substrate is prepared including a mixed layer along which extends one surface portion and is formed of first areas and adjacent different second areas of amorphous material, the second areas forming at least part of the free surface of the first substrate. The first substrate is bonded to the other surface portion with the same crystal orientation as the first surface portion, by molecular bonding over at least the amorphous areas. A solid phase recrystallization of at least part of the amorphous areas according to the crystal orientation of the first substrate is selectively carried and the two surface portions are separated.

摘要翻译： 制造混合基板的方法包括制备单晶第一基板以获得两个表面部分。 制备临时衬底，其包括混合层，沿其延伸一个表面部分并且由第一区域和相邻的不同第二区域的非晶材料形成，第二区域形成第一衬底的至少部分自由表面。 第一衬底通过在至少非晶区上分子键合而与第一表面部分具有相同的晶体取向而与另一表面部分结合。 选择性地承载根据第一基板的晶体取向的至少一部分非晶区域的固相重结晶，并分离两个表面部分。

公开(公告)号：US20090325335A1

公开(公告)日：2009-12-31

申请号：US12488854

申请日：2009-06-22

申请人： François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

发明人： François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

IPC分类号： H01L21/302 ,  H01L21/02

CPC分类号： B81C1/00595 ,  B81B2201/0271 ,  B81C2201/0109 ,  B81C2201/014

摘要： The invention relates to a method of making a component from a heterogeneous substrate comprising first and second portions in at least one monocrystalline material, and a sacrificial layer constituted by at least one stack of at least one layer of monocrystalline Si situated between two layers of monocrystalline SiGe, the stack being disposed between said first and second portions of monocrystalline material, wherein the method consists in etching said stack by making: e) at least one opening in the first and/or second portion and the first and/or second layer of SiGe so as to reach the layer of Si; and f) eliminating all or part of the layer of Si.

摘要翻译： 本发明涉及一种从包含至少一种单晶材料中的第一和第二部分的异质衬底制备组分的方法，以及由位于两层单晶之间的至少一层单晶硅的至少一个叠层构成的牺牲层 SiGe，堆叠设置在单晶材料的第一和第二部分之间，其中该方法包括通过以下步骤蚀刻所述堆叠：e）在第一和/或第二部分中的至少一个开口，以及第一和/ SiGe，以达到Si层; 和f）消除Si的全部或部分层。