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1.发明授权Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT 有权具有集成在三维中并具有动态可调阈值电压VT的晶体管的电路公开(公告)号：US08183630B2
公开(公告)日：2012-05-22
申请号：US12474851
申请日：2009-05-29
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.
摘要翻译： 一种微电子器件，包括：由一叠层叠层的衬底，位于所述堆叠的给定电平处的至少一个第一晶体管，位于所述叠层的第二电平以上的至少一个第二晶体管，高于所述给定电平，所述第一晶体管 包括与第二晶体管的沟道区相对的栅电极，第一晶体管和第二晶体管被绝缘区隔开，所述绝缘区由几种不同的介电材料构成，包括第一电介质材料和第二电介质材料。
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2.发明申请CIRCUIT WITH TRANSISTORS INTEGRATED IN THREE DIMENSIONS AND HAVING A DYNAMICALLY ADJUSTABLE THRESHOLD VOLTAGE VT 有权具有集成在三维尺寸并具有动态可调节阈值电压VT的晶体管的电路公开(公告)号：US20090294822A1
公开(公告)日：2009-12-03
申请号：US12474851
申请日：2009-05-29
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A microelectronic device comprising: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by means of an insulating zone, said insulating zone having, in a first region between said gate of said first transistor and said channel of said second transistor, a composition and thickness provided so as to enable a coupling between the gate electrode of the first transistor and the channel of the second transistor, said insulating zone comprising a second region around the first region, between the access zones of the first and the second transistor of thickness and composition different to those of said first region.
摘要翻译： 一种微电子器件，包括：由一叠层叠层的衬底，位于所述堆叠的给定电平的至少一个第一晶体管，位于所述叠层的第二电平以上的至少一个第二晶体管，高于所述给定电平，所述第一晶体管 包括与所述第二晶体管的沟道区相对的栅电极，所述第一晶体管和所述第二晶体管通过绝缘区隔开，所述绝缘区在所述第一晶体管的所述栅极和所述第一晶体管的所述沟道之间的第一区域中 所述第二晶体管的组成和厚度设置成使得能够在所述第一晶体管的栅电极和所述第二晶体管的沟道之间的耦合，所述绝缘区包括所述第一区周围的第二区， 以及第二晶体管的厚度和组成不同于所述第一区域的晶体管。
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3.发明申请INTEGRATED CIRCUIT WITH ELECTROSTATICALLY COUPLED MOS TRANSISTORS AND METHOD FOR PRODUCING SUCH AN INTEGRATED CIRCUIT 有权具有静电耦合MOS晶体管的集成电路和用于生产这种集成电路的方法公开(公告)号：US20110147849A1
公开(公告)日：2011-06-23
申请号：US12868488
申请日：2010-08-25
IPC分类号： H01L27/088 , H01L21/98
CPC分类号： H01L27/1104 , H01L21/8221 , H01L27/0688 , H01L27/11
摘要： An integrated circuit including: a first transistor; a second transistor, arranged on the first transistor, whereof a channel region is formed in a semiconductor layer including two approximately parallel primary faces; a portion of an electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged between the portion of the electrically conductive material and the channel region of the second transistor; and in which the section of the channel region of the second transistor is included in the section of the portion of the electrically conductive material, and the channel region of the second transistor is arranged between the portion of the electrically conductive material and a gate of the second transistor.
摘要翻译： 一种集成电路，包括：第一晶体管; 第二晶体管，布置在第一晶体管上，沟道区形成在包括两个近似平行的主面的半导体层中; 导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且其中第二晶体管的沟道区域的部分包括在导电材料部分的部分中，并且第二晶体管的沟道区域被布置在导电材料的部分和栅极之间 第二晶体管。
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4.发明授权公开(公告)号：US08853785B2
公开(公告)日：2014-10-07
申请号：US12868488
申请日：2010-08-25
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L21/8221 , H01L27/0688 , H01L27/11
摘要： An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.
摘要翻译： 一种集成电路，至少包括：第一MOS晶体管; 配置在所述第一MOS晶体管上的第二MOS晶体管，所述第二MOS晶体管在至少一个包含两个近似平行的主面的半导体层中包括沟道区; 至少一个导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 至少布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且在与半导体层的两个主面平行的平面中的第二晶体管的沟道区域的一部分被包括在投影在所述平面中的导电材料部分的一部分中。
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5.发明授权SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable 有权SRAM存储单元具有以多个级别集成的晶体管，其阈值电压VT可动态调整公开(公告)号：US08013399B2
公开(公告)日：2011-09-06
申请号：US12466733
申请日：2009-05-15
IPC分类号： H01L27/088
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are connected to a word line and are arranged between a first bit line and a first storage node and a second bit line and a second storage node, respectively; and a second plurality of transistors forming a flip-flop and situated at least one other level of the stack, beneath said given level, wherein the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by an insulating region provided to enable coupling of said gate electrode and said channel region.
摘要翻译： 一种静态随机存取存储单元，其在由层叠层所覆盖的衬底上，包括：第一多个晶体管，位于堆叠的给定电平，其中至少一个第一存取晶体管和至少一个第二存取晶体管连接 分别布置在第一位线和第一存储节点以及第二位线和第二存储节点之间; 以及第二多个晶体管，其形成触发器并且位于所述给定电平以下的所述堆叠的至少另一个电平，其中所述第二多个晶体管的晶体管每个包括位于与所述晶体管的晶体管的沟道区相对的栅电极 所述第一多个晶体管并且由所述沟道区域与被设置成能够耦合所述栅极电极和所述沟道区域的绝缘区域分离。
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6.发明申请SRAM MEMORY CELL HAVING TRANSISTORS INTEGRATED AT SEVERAL LEVELS AND THE THRESHOLD VOLTAGE VT OF WHICH IS DYNAMICALLY ADJUSTABLE 有权具有集成在几个级别的晶体管的SRAM存储单元和动态调整的阈值电压VT公开(公告)号：US20090294861A1
公开(公告)日：2009-12-03
申请号：US12466733
申请日：2009-05-15
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , H01L27/0688 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A non-volatile random access memory cell which, on a substrate surmounted by a stack of layers, comprises:a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor, which are arranged between a first bit line and a first storage node, and between a second bit line and a second storage node, respectively, the first access transistor and the second access transistor having a gate connected to a word line,a second plurality of transistors forming a flip-flop and situated at, at least one other level of the stack, beneath said given level,the transistors of the second plurality of transistors each comprising a gate electrode situated opposite a channel region of a transistor of the first plurality of transistors and separated from this channel region by means of an insulating region provided to enable coupling of said gate electrode and said channel region.
摘要翻译： 一种非易失性随机存取存储单元，其在由层叠层所覆盖的衬底上，包括：第一多个晶体管，位于堆叠的给定电平处，其中至少一个第一存取晶体管和至少一个第二存取晶体管 ，其分别布置在第一位线和第一存储节点之间，以及第二位线和第二存储节点之间，第一存取晶体管和第二存取晶体管具有连接到字线的栅极，第二多个 形成触发器并且位于所述堆叠的至少另一个层级下面的所述给定电平以下的所述第二多个晶体管的晶体管分别包括与所述第一多个晶体管的沟道区相对的栅电极 的晶体管，并且通过提供用于使得所述栅极电极和所述沟道区域耦合的绝缘区域与该沟道区域分离。
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公开(公告)号：US07678635B2
公开(公告)日：2010-03-16
申请号：US12030672
申请日：2008-02-13
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/28123 , H01L29/66325 , H01L29/66659 , H01L29/7391 , H01L29/78
摘要： Method of producing a transistor, comprising in particular the steps of: producing a first etching mask on a gate layer, one edge of the first mask forming a pattern of the first edge of a gate of the transistor, etching the gate layer according to the first etching mask, first ion implantation in a part of the substrate not covered by the gate layer, trimming the first etching mask over a length equal to a gate length of the transistor, producing a second etching mask on the gate layer, removing the first etching mask etching the gate layer according to the second etching mask, second ion implantation in another part of the substrate.
摘要翻译： 制造晶体管的方法，其特别包括以下步骤：在栅极层上制造第一蚀刻掩模，第一掩模的一个边缘形成晶体管的栅极的第一边缘的图案，根据该栅极层蚀刻栅极层 第一蚀刻掩模，在未被栅极层覆盖的衬底的一部分中的第一离子注入，在等于晶体管的栅极长度的长度上修整第一蚀刻掩模，在栅极层上产生第二蚀刻掩模，去除第一蚀刻掩模 蚀刻掩模根据第二蚀刻掩模蚀刻栅极层，在衬底的另一部分中进行第二离子注入。
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8.发明申请Memory cell provided with dual-gate transistors, with independent asymmetric gates 有权具有双栅极晶体管的存储单元，具有独立的非对称栅极公开(公告)号：US20080175039A1
公开(公告)日：2008-07-24
申请号：US12005666
申请日：2007-12-26
申请人： Olivier Thomas , Maud Vinet
发明人： Olivier Thomas , Maud Vinet
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104 , H01L29/785
摘要： The invention concerns a random access memory cell comprising: at least one first plurality of symmetrical dual-gate transistors (TL1T, TL1F, TD1T, TD1F, TL2T, TL2F) forming a flip-flop, at least a first asymmetric dual-gate access transistor (TA1T, TAW1T) and at least a second asymmetric dual-gate access transistor (TA1F, TAW1F) disposed respectively between a first bit line (BLT, WBLT) and a first storage node (T), and between a second bit line (BLF, WBLF) and a second storage node (F), a first gate of the first access transistor (TA1T, TAW1T) and a first gate of the second access transistor (TA1F, TAW1F) being connected to a first word line (WL, WWL) able to route a biasing signal, a second gate (TA1F, TAW1F) of the first access transistor connected to the second storage node (F) and a second gate of the second access transistor connected to the first storage node (T).
摘要翻译： 本发明涉及一种随机存取存储器单元，包括：至少一个第一多个对称双栅极晶体管（TL 1，T 1，T 1，T 1 T 形成触发器的至少第一不对称双重元件，第一非对称双重元件，第二非对称双重元件 至少一个第二非对称双栅极存取晶体管（TA 1，...，T 1） 分别设置在第一位线（BL ，WBL＆gt; T＆gt;）和第一存储节点（T）之间，以及 第一存取晶体管的第一栅极（TA1
T < / SUB>，TAW 1 T）和第二存取晶体管（TA 1 F 1，TAW 1 F 1）的第一栅极连接到 能够路由偏置信号的第一字线（WL，WWL），第一存取转发器的第二门（TA 1，F 1，TAW 1＆lt; F 1） 存储器连接到第二存储节点（F）和连接到第一存储节点（T）的第二存取晶体管的第二栅极。 -
9.发明授权Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate 有权制造不对称双栅极晶体管的方法，通过该方法可以在同一衬底上制造不对称和对称双栅极晶体管公开(公告)号：US08232168B2
公开(公告)日：2012-07-31
申请号：US12521311
申请日：2007-12-28
申请人： Maud Vinet , Olivier Thomas , Olivier Rozeau , Thierry Poiroux
发明人： Maud Vinet , Olivier Thomas , Olivier Rozeau , Thierry Poiroux
IPC分类号： H01L21/336
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L29/78645
摘要： A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.
摘要翻译： 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在至少包括构成为形成双栅极晶体管的第一栅极的第一块的至少一个衬底上形成一个或多个结构，并且至少 第二块，其被配置为形成所述双栅极的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与所述半导体区分离 并且b）使用相对于第一块选择性的至少一种植入，在所述结构中掺杂至少一个给定结构的第二块中的至少一个或多个半导体区域，所述第二块被硬掩模覆盖， 硬掩模的临界尺寸大于第二块的临界尺寸。
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公开(公告)号：US07812410B2
公开(公告)日：2010-10-12
申请号：US12168417
申请日：2008-07-07
申请人： Michael Collonge , Maud Vinet , Olivier Thomas
发明人： Michael Collonge , Maud Vinet , Olivier Thomas
IPC分类号： H01L27/20 , H01L41/04 , H01L41/083
CPC分类号： G11C23/00 , B82Y10/00 , G11C2213/17 , H01L29/515 , H01L29/78654
摘要： A microelectronic device, including at least one transistor including: on a substrate, a semiconductor zone with a channel zone covered with a gate dielectric zone, a mobile gate, suspended above the gate dielectric zone and separated from the gate dielectric zone by an empty space, which the gate is located at an adjustable distance from the gate dielectric zone, and a piezoelectric actuation device including a stack formed by at least one layer of piezoelectric material resting on a first biasing electrode, and a second biasing electrode resting on the piezoelectric material layer, wherein the gate is attached to the first biasing electrode and is in contact with the first biasing electrode, and the piezoelectric actuation device is configured to move the gate with respect to the channel zone.
摘要翻译： 一种微电子器件，包括至少一个晶体管，其包括：在衬底上，具有覆盖有栅极介电区的沟道区的半导体区，悬浮在栅极介电区上方的移动栅极，并与栅极介电区隔开空位 栅极位于与栅极介电区域可调节的距离处，以及压电致动装置，其包括由至少一层静电在第一偏置电极上的压电材料形成的叠层，以及沉积在压电材料上的第二偏置电极 层，其中所述栅极附接到所述第一偏置电极并且与所述第一偏置电极接触，并且所述压电致动装置被配置为相对于所述沟道区移动所述栅极。
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