公开(公告)号：US20110147849A1

公开(公告)日：2011-06-23

申请号：US12868488

申请日：2010-08-25

Applicant: Emmanuel AUGENDRE ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

Inventor： Emmanuel AUGENDRE ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

IPC: H01L27/088 ,  H01L21/98

CPC classification number: H01L27/1104 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11

Abstract: An integrated circuit including: a first transistor; a second transistor, arranged on the first transistor, whereof a channel region is formed in a semiconductor layer including two approximately parallel primary faces; a portion of an electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged between the portion of the electrically conductive material and the channel region of the second transistor; and in which the section of the channel region of the second transistor is included in the section of the portion of the electrically conductive material, and the channel region of the second transistor is arranged between the portion of the electrically conductive material and a gate of the second transistor.

Abstract translation: 一种集成电路，包括：第一晶体管; 第二晶体管，布置在第一晶体管上，沟道区形成在包括两个近似平行的主面的半导体层中; 导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且其中第二晶体管的沟道区域的部分包括在导电材料部分的部分中，并且第二晶体管的沟道区域被布置在导电材料的部分和栅极之间 第二晶体管。

公开(公告)号：US07879690B2

公开(公告)日：2011-02-01

申请号：US12413130

申请日：2009-03-27

Applicant: Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

Inventor： Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L21/76254

Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.

Abstract translation: 通过形成包括形成衬底的板，连续绝缘层和半导体层的层叠均匀结构，来产生具有不同图案的绝缘体半导体型微结构。 连续绝缘层是至少三个基本层的堆叠，包括底部基本层，至少一个中间基本层和覆盖半导体层的顶部基本层，其中底部基本层和顶部基本层中的至少一个 层是绝缘材料。 在层叠的均匀结构中，通过修改其中一个图案中的至少一个基本层来区分至少两个图案，使得元件层在两个图案之间具有显着不同的物理或化学性质，其中至少一个 底部和顶部基本层是保持不变的绝缘材料。

公开(公告)号：US20110001184A1

公开(公告)日：2011-01-06

申请号：US12865549

申请日：2009-02-11

Applicant: Francois Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

Inventor： Francois Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/42348 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/792

Abstract: An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

Abstract translation: 一种用于生产电子组件的电子组件和相关联的方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，其中在预定的第一深度处形成第一捕集区。 第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。 来自第一晶体管的有用信息包括该晶体管内的电荷传输。 可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。

公开(公告)号：US08853785B2

公开(公告)日：2014-10-07

申请号：US12868488

申请日：2010-08-25

Applicant: Emmanuel Augendre ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

Inventor： Emmanuel Augendre ,  Maud Vinet ,  Laurent Clavelier ,  Perrine Batude

IPC: H01L27/088

CPC classification number: H01L27/1104 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11

Abstract: An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.

Abstract translation: 一种集成电路，至少包括：第一MOS晶体管; 配置在所述第一MOS晶体管上的第二MOS晶体管，所述第二MOS晶体管在至少一个包含两个近似平行的主面的半导体层中包括沟道区; 至少一个导电材料的一部分电连接到第一晶体管的栅极并且布置在第一晶体管的栅极和第二晶体管的沟道区之间; 至少布置在所述导电材料的所述部分和所述第二晶体管的沟道区之间的电介质层; 并且在与半导体层的两个主面平行的平面中的第二晶体管的沟道区域的一部分被包括在投影在所述平面中的导电材料部分的一部分中。

公开(公告)号：US08809964B2

公开(公告)日：2014-08-19

申请号：US12865549

申请日：2009-02-11

Applicant: François Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

Inventor： François Andrieu ,  Emmanuel Augendre ,  Laurent Clavelier ,  Marek Kostrzewa

IPC: H01L21/336 ,  H01L29/792

CPC classification number: H01L29/42348 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/792

Abstract: An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.

Abstract translation: 一种用于生产电子组件的电子组件和相关方法，包括至少具有可调阈值电压的第一晶体管的半导体层被连接到绝缘体层，并且其中在预定的第一深度形成第一捕集区。 第一捕获区至少在第一晶体管的沟道下方延伸，并且包括具有比第一捕获区外的阱的密度更高密度的陷阱，使得半导体层和第一捕获区电容耦合。 来自第一晶体管的有用信息包括该晶体管内的电荷传输。 可以形成第二捕获区，其至少在通过第二注入形成的第二晶体管的沟道下方延伸，所述第二晶体管具有不同于用于形成第一捕获区的能量和/或剂量和/或原子的能量和/或原子。

公开(公告)号：US20090246946A1

公开(公告)日：2009-10-01

申请号：US12413130

申请日：2009-03-27

Applicant: Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

Inventor： Emmanuel Augendre ,  Thomas Ernst ,  Marek Kostrzewa ,  Hubert Moriceau

IPC: H01L21/762

CPC classification number: H01L21/76254

Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.

Abstract translation: 通过形成包括形成衬底的板，连续绝缘层和半导体层的层叠均匀结构，来产生具有不同图案的绝缘体半导体型微结构。 连续绝缘层是至少三个基本层的堆叠，包括底部基本层，至少一个中间基本层和覆盖半导体层的顶部基本层，其中底部基本层和顶部基本层中的至少一个 层是绝缘材料。 在层叠的均匀结构中，通过修改其中一个图案中的至少一个基本层来区分至少两个图案，使得元件层在两个图案之间具有显着不同的物理或化学特性，其中至少一个 底部和顶部基本层是保持不变的绝缘材料。

公开(公告)号：US06855605B2

公开(公告)日：2005-02-15

申请号：US10286427

申请日：2002-10-30

Applicant: Malgorzata Jurczak ,  Rita Rooyackers ,  Emmanuel Augendre ,  Goncal Badenes

Inventor： Malgorzata Jurczak ,  Rita Rooyackers ,  Emmanuel Augendre ,  Goncal Badenes

IPC: H01L21/28 ,  H01L21/3215 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/425 ,  H01L29/76 ,  H01L31/062

CPC classification number: H01L21/82385 ,  H01L21/32155

Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.

Abstract translation: 在相同的器件材料中在半导体器件中形成具有不同厚度或层高的层的方法包括在器件层的选定区域中形成器件材料层或栅极电极层一次性部件。 可以通过将所选择的区域掺杂到期望的深度d来形成一次性部件。 通过去除一次性部件，可以在各个装置的图案化之后调整或调制该装置层的沉积厚度t。