公开(公告)号：US09671973B2

公开(公告)日：2017-06-06

申请号：US14651091

申请日：2013-12-20

Applicant: Empire Technology Development LLC

Inventor： Tong Zhang

IPC: G11C29/00 ,  G06F3/06 ,  G11C16/34 ,  G11C29/12 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1012 ,  G06F11/1068 ,  G11C16/349 ,  G11C29/12 ,  G11C29/52 ,  G11C29/70 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Technologies are generally described for systems, devices, and methods effective to operate a memory device. A memory controller may compress initial data to produce compressed data. The memory controller may select a storage block in the memory device. The memory controller may identify one or more positions of defective cells in the selected storage block. The memory controller may manipulate the compressed data based on the identified one or more positions to produce manipulated data. The memory controller may store the manipulated data in the selected storage block.

公开(公告)号：US09805813B2

公开(公告)日：2017-10-31

申请号：US14649505

申请日：2013-08-30

Applicant: Empire Technology Development LLC

Inventor： Tong Zhang

IPC: G11C29/00 ,  G11C16/34 ,  G11C16/30 ,  G11C7/14 ,  G11C29/02 ,  G06F11/10 ,  G06F11/07 ,  G11C16/26 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C16/3495 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/1048 ,  G11C7/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/0411

Abstract: Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory.

公开(公告)号：US09513990B2

公开(公告)日：2016-12-06

申请号：US14494319

申请日：2014-09-23

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Tong Zhang

IPC: H03M13/00 ,  G06F11/10 ,  H04L1/00

CPC classification number: G06F11/1016 ,  G06F11/1048 ,  H04L1/0083

Abstract: Technologies are generally described for systems, devices and methods relating to generation of an instruction to store data. Read unit length information are identified for data. The read unit length information includes a read unit length. The data has a data length. The data length implicates a first error correction code of a first size. The read unit length relates to an amount of the data to be read as a unit from a memory. The read unit length is different from the data length. A second error correction code is determined to store the data. The second error correction code is based on the read unit length information. The second error correction code has a second size. The instruction is effective to store the second error correction code in association with the data in the memory.

Abstract translation: 通常描述与生成用于存储数据的指令相关的系统，设备和方法的技术。 为数据识别读取单位长度信息。 读取单位长度信息包括读取单位长度。 数据具有数据长度。 数据长度涉及第一大小的第一纠错码。 读取单位长度与从存储器单元读取的数据量有关。 读取单位长度与数据长度不同。 确定第二个纠错码来存储数据。 第二纠错码基于读取的单位长度信息。 第二个纠错码具有第二个大小。 该指令有效地存储与存储器中的数据相关联的第二纠错码。