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    Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure
    1.
    发明申请
    Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure 有权
    操作具有氧化物/氮化物多层绝缘结构的非易失性存储单元的方法

    公开(公告)号：US20080157184A1

    公开(公告)日：2008-07-03

    申请号：US11649348

    申请日：2007-01-03

    申请人： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

    发明人： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513

    摘要： A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.

    摘要翻译： 公开了一种通过向栅极施加足以使栅极向电荷存储层进行空穴隧道的正电压来操作存储单元的方法。 该方法应用于包括半导体层的存储单元，该半导体层具有设置在半导体层的表面下方并由沟道区分隔开的至少两个源极/漏极区域。 存储单元还具有设置在沟道区域上方的下绝缘层; 电荷存储层，其设置在所述下绝缘层的上方; 设置在电荷存储层上方的上绝缘多层结构。 上绝缘多层结构包括下介电层和设置在下介电层上的上氮化物层，并且存储单元具有设置在上绝缘多层结构上方的栅极。

    ONO formation of semiconductor memory device and method of fabricating the same
    5.
    发明授权
    ONO formation of semiconductor memory device and method of fabricating the same 有权
    ONO形成半导体存储器件及其制造方法

    公开(公告)号：US07763935B2

    公开(公告)日：2010-07-27

    申请号：US11159269

    申请日：2005-06-23

    申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

    摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.

    摘要翻译： 一种制造非易失性存储器件的方法至少包括以下步骤。 首先，提供形成有底部电介质层的基板。 然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。 该结构被热退火以推动间隔开的掺杂区域向外扩散。 退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。 最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

    ONO formation of semiconductor memory device and method of fabricating the same
    6.
    发明申请
    ONO formation of semiconductor memory device and method of fabricating the same 有权
    ONO形成半导体存储器件及其制造方法

    公开(公告)号：US20060292800A1

    公开(公告)日：2006-12-28

    申请号：US11159269

    申请日：2005-06-23

    申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

    摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.

    摘要翻译： 一种制造非易失性存储器件的方法至少包括以下步骤。 首先，提供形成有底部电介质层的基板。 然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。 该结构被热退火以推动间隔开的掺杂区域向外扩散。 退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。 最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

    SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE 有权
    具有改进位线电容的半导体结构

    公开(公告)号：US20140054535A1

    公开(公告)日：2014-02-27

    申请号：US13594353

    申请日：2012-08-24

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    IPC分类号： H01L47/00

    CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

    摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

    摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

    Dual-gate, sonos, non-volatile memory cells and arrays thereof
    9.
    发明授权
    Dual-gate, sonos, non-volatile memory cells and arrays thereof 有权
    双栅极，超声波，非易失性存储单元及其阵列

    公开(公告)号：US07973366B2

    公开(公告)日：2011-07-05

    申请号：US11352788

    申请日：2006-02-13

    申请人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

    摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

    摘要翻译： 存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。

    Semiconductor structure with improved capacitance of bit line
    10.
    发明授权
    Semiconductor structure with improved capacitance of bit line 有权
    具有改善位线电容的半导体结构

    公开(公告)号：US08704205B2

    公开(公告)日：2014-04-22

    申请号：US13594353

    申请日：2012-08-24

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    IPC分类号： H01L47/00

    CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

    摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

    摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。