利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

60 条记录 (耗时 0.031 秒)

    Dual-gate, sonos, non-volatile memory cells and arrays thereof
    2.
    发明授权
    Dual-gate, sonos, non-volatile memory cells and arrays thereof 有权
    双栅极，超声波，非易失性存储单元及其阵列

    公开(公告)号：US07973366B2

    公开(公告)日：2011-07-05

    申请号：US11352788

    申请日：2006-02-13

    申请人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

    摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

    摘要翻译： 存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。

    SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE 有权
    具有改进位线电容的半导体结构

    公开(公告)号：US20140054535A1

    公开(公告)日：2014-02-27

    申请号：US13594353

    申请日：2012-08-24

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    IPC分类号： H01L47/00

    CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

    摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

    摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

    Semiconductor structure with improved capacitance of bit line
    4.
    发明授权
    Semiconductor structure with improved capacitance of bit line 有权
    具有改善位线电容的半导体结构

    公开(公告)号：US08704205B2

    公开(公告)日：2014-04-22

    申请号：US13594353

    申请日：2012-08-24

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    IPC分类号： H01L47/00

    CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

    摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

    摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

    Memory and manufacturing method thereof
    9.
    发明申请
    Memory and manufacturing method thereof 有权
    其记忆及其制造方法

    公开(公告)号：US20090057748A1

    公开(公告)日：2009-03-05

    申请号：US11892980

    申请日：2007-08-29

    申请人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

    发明人： Erh-Kun Lai ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

    IPC分类号： H01L29/788 ,  H01L21/8239

    CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578

    摘要： A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage. The first buried diffusion and the second buried diffusion are separately disposed in the surface of the polysilicon layer. The charge storage structure is disposed on the polysilicon layer and positioned between the first buried diffusion and the second buried diffusion. The gate is disposed on the charge storage structure.

    摘要翻译： 提供了一种存储器及其制造方法。 存储器包括电介质层，多晶硅层，第一掩埋扩散层，第二掩埋扩散层，电荷存储结构和栅极。 多晶硅层设置在电介质层上并电连接至少一个电压。 第一掩埋扩散部和第二掩埋扩散部分别设置在多晶硅层的表面。 电荷存储结构设置在多晶硅层上并且位于第一掩埋扩散区和第二掩埋扩散区之间。 栅极设置在电荷存储结构上。