INVALIDATING TRANSLATION LOOKASIDE BUFFER ENTRIES IN A VIRTUAL MACHINE SYSTEM
    3.
    发明申请
    INVALIDATING TRANSLATION LOOKASIDE BUFFER ENTRIES IN A VIRTUAL MACHINE SYSTEM 失效
    在虚拟机系统中隐藏翻译预览缓冲区入口

    公开(公告)号:US20130212313A1

    公开(公告)日:2013-08-15

    申请号:US13837648

    申请日:2013-03-15

    IPC分类号: G06F12/10

    摘要: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

    摘要翻译: 本发明的一个实施例是使翻译后备缓冲器(TLB)中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时,每个TLB条目与虚拟机扩展(VMX)标签字相关联,指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机(VM)中的执行之一,而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合,它由(1)可能为空的操作集合组合,使一组可变数量的TLB条目无效,(2)一组可能的空白操作,使一个TLB无效 条目,(3)使多个TLB条目无效的可能的一组操作,(4)启用和禁用虚拟存储器的使用的可能的一组可能的空操作,以及(5)配置物理的可能的一组操作 地址大小,页面大小或其他虚拟内存系统行为,以改变物理机器解释TLB条目的方式。

    INVALIDATING TRANSLATION LOOKASIDE BUFFER ENTRIES IN A VIRTUAL MACHINE (VM) SYSTEM
    4.
    发明申请
    INVALIDATING TRANSLATION LOOKASIDE BUFFER ENTRIES IN A VIRTUAL MACHINE (VM) SYSTEM 有权
    在虚拟机(VM)系统中隐藏翻译预览缓冲区入口

    公开(公告)号:US20120117300A1

    公开(公告)日:2012-05-10

    申请号:US12959109

    申请日:2010-12-02

    IPC分类号: G06F12/08

    摘要: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

    摘要翻译: 本发明的一个实施例是使翻译后备缓冲器(TLB)中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时,每个TLB条目与虚拟机扩展(VMX)标签字相关联,指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机(VM)中的执行之一,而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合,它由(1)可能为空的操作集合组合,使一组可变数量的TLB条目无效,(2)一组可能的空白操作,使一个TLB无效 条目,(3)使多个TLB条目无效的可能的一组操作,(4)启用和禁用虚拟存储器的使用的可能的一组可能的空操作,以及(5)配置物理的可能的一组操作 地址大小,页面大小或其他虚拟内存系统行为,以改变物理机器解释TLB条目的方式。

    Invalidating translation lookaside buffer entries in a virtual machine (VM) system
    5.
    发明授权
    Invalidating translation lookaside buffer entries in a virtual machine (VM) system 有权
    使虚拟机(VM)系统中的翻译后备缓冲区条目无效

    公开(公告)号:US08543772B2

    公开(公告)日:2013-09-24

    申请号:US12959109

    申请日:2010-12-02

    IPC分类号: G06F12/08

    摘要: One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

    摘要翻译: 本发明的一个实施例是使翻译后备缓冲器(TLB)中的条目无效的技术。 处理器中的TLB具有多个TLB条目。 当执行无效操作时,每个TLB条目与虚拟机扩展(VMX)标签字相关联,指示相关联的TLB条目是否根据处理器模式而无效。 处理器模式是虚拟机(VM)中的执行之一,而不是虚拟机中的执行。 无效操作属于一个无效的无效操作集合,它由(1)可能为空的操作集合组合,使一组可变数量的TLB条目无效,(2)一组可能的空白操作,使一个TLB无效 条目,(3)使多个TLB条目无效的可能的一组操作,(4)启用和禁用虚拟存储器的使用的可能的一组可能的空操作,以及(5)配置物理的可能的一组操作 地址大小,页面大小或其他虚拟内存系统行为,以改变物理机器解释TLB条目的方式。

    Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment
    7.
    发明申请
    Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment 有权
    在多处理器环境中单方面加载安全操作系统的装置和方法

    公开(公告)号:US20070192577A1

    公开(公告)日:2007-08-16

    申请号:US11340181

    申请日:2006-01-24

    IPC分类号: G06F15/177

    CPC分类号: G06F21/57

    摘要: An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.

    摘要翻译: 描述了在多处理器环境内单方面加载安全操作系统的装置和方法。 该方法包括当检测到当前活动的负载安全区域操作时忽略接收到的负载安全区域指令。 否则,响应于接收到的负载安全区域指令,引导存储器保护元件以形成安全存储器环境。 一旦定向,就禁止对一个或多个受保护的存储器区域进行未经授权的读/写访问。 最后,一个或多个受保护的存储器区域的加密散列值作为安全的软件识别值存储在摘要信息库中。 一旦存储,外部代理可以请求访问数字签名的软件标识值以建立安全存储器环境内的安全软件的安全验证。