公开(公告)号：US08601233B2

公开(公告)日：2013-12-03

申请号：US13658752

申请日：2012-10-23

申请人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron B. Rust ,  Sebastian Schoenberg

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron B. Rust ,  Sebastian Schoenberg

IPC分类号： G11C15/00

CPC分类号： G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US08099581B2

公开(公告)日：2012-01-17

申请号：US12495555

申请日：2009-06-30

申请人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Dion Rodgers ,  Rajesh Madukkaraumukumana ,  Camron Rust ,  Sebastian Schoenberg

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Dion Rodgers ,  Rajesh Madukkaraumukumana ,  Camron Rust ,  Sebastian Schoenberg

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US20090089527A1

公开(公告)日：2009-04-02

申请号：US11864477

申请日：2007-09-28

申请人： Sebastian Schoenberg ,  Steven M. Bennett ,  Andrew V. Anderson

发明人： Sebastian Schoenberg ,  Steven M. Bennett ,  Andrew V. Anderson

IPC分类号： G06F12/14

CPC分类号： G06F9/45558 ,  G06F2009/45579

摘要： Embodiments of apparatuses, methods, and systems for executing a protected device model in a virtual machine are disclosed. In one embodiment, an apparatus includes recognition logic, memory management logic, control logic, and execution logic. The recognition logic is to recognize an indication, during execution of first code on a virtual machine, that the first code is attempting to access a device. The memory management logic is to prevent the virtual machine from accessing a portion of memory during execution of the first code, and to allow the virtual machine to access the portion of memory in response to the indication. The control logic is to transfer control of the apparatus from the first code to second code stored in the portion of memory, without exiting the virtual machine. The execution logic is to execute the second code to model the device.

摘要翻译： 公开了用于在虚拟机中执行受保护设备模型的装置，方法和系统的实施例。 在一个实施例中，装置包括识别逻辑，存储器管理逻辑，控制逻辑和执行逻辑。 识别逻辑是在虚拟机上执行第一代码期间识别出第一代码尝试访问设备的指示。 存储器管理逻辑是在执行第一代码期间防止虚拟机访问存储器的一部分，并且允许虚拟机响应于指示访问存储器的一部分。 控制逻辑是将装置的控制从第一代码传送到存储在存储器部分中的第二代码，而不退出虚拟机。 执行逻辑是执行第二个代码来对设备进行建模。

公开(公告)号：US07506121B2

公开(公告)日：2009-03-17

申请号：US11322757

申请日：2005-12-30

申请人： Gilbert Neiger ,  Andrew V. Anderson ,  Steven M. Bennett ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Rajesh S. Parthasarathy ,  Sebastian Schoenberg

发明人： Gilbert Neiger ,  Andrew V. Anderson ,  Steven M. Bennett ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Rajesh S. Parthasarathy ,  Sebastian Schoenberg

IPC分类号： G06F12/00

CPC分类号： G06F12/1441 ,  G06F12/145 ,  G06F2009/45587

摘要： Embodiments of apparatuses, methods, and systems for guests to access memory mapped devices are disclosed. In one embodiment, an apparatus includes evaluation logic and exit logic. The evaluation logic is to determine, in response to an attempt of a guest to access a device using a memory address mapped to the device and based on an access type, whether the access is allowed. The exit logic is to transfer control to a host if the evaluation logic determines that the access is not allowed.

摘要翻译： 公开了访客访问存储器映射设备的装置，方法和系统的实施例。 在一个实施例中，装置包括评估逻辑和退出逻辑。 评估逻辑是为了响应于访客访问使用映射到设备的存储器地址并基于访问类型访问设备的尝试，确定访问是否被允许。 如果评估逻辑确定不允许访问，退出逻辑将控制传送到主机。

公开(公告)号：US20070157197A1

公开(公告)日：2007-07-05

申请号：US11323114

申请日：2005-12-30

申请人： Gilbert Neiger ,  Rajesh Madukkarumukumana ,  Richard Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven Bennett ,  Andrew Anderson ,  Erik Cota-Robles

发明人： Gilbert Neiger ,  Rajesh Madukkarumukumana ,  Richard Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven Bennett ,  Andrew Anderson ,  Erik Cota-Robles

IPC分类号： G06F9/455

CPC分类号： G06F13/24 ,  G06F9/45533 ,  G06F9/4812

摘要： Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

摘要翻译： 公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。 在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。 交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。 如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

公开(公告)号：US07020738B2

公开(公告)日：2006-03-28

申请号：US10676737

申请日：2003-09-30

申请人： Gilbert Neiger ,  Stephen Chou ,  Erik Cota-Robles ,  Stalinselvaraj Jevasingh ,  Alain Kagi ,  Michael Kozuch ,  Richard Uhlig ,  Sebastian Schoenberg

发明人： Gilbert Neiger ,  Stephen Chou ,  Erik Cota-Robles ,  Stalinselvaraj Jevasingh ,  Alain Kagi ,  Michael Kozuch ,  Richard Uhlig ,  Sebastian Schoenberg

IPC分类号： G06F13/00

CPC分类号： G06F9/45558 ,  G06F12/0284 ,  G06F12/109 ,  G06F2009/45583

摘要： One embodiment of the invention is method for resolving address space conflicts between a virtual machine monitor and a guest operating system. The method includes allocating an address space for the operating system and an address space for the monitor. The method also includes mapping a portion of the monitor into the address space allocated for the operating system and the address space allocated for the monitor, and locating another portion of the monitor in the address space allocated for the monitor. The method also includes detecting that the operating system attempts to access a region occupied by the portion of the monitor within the address space allocated for the operating system, and relocating that portion of the monitor within that address space to allow the operating system to access the region previously occupied by that portion of the monitor.

摘要翻译： 本发明的一个实施例是用于解决虚拟机监视器和客户操作系统之间的地址空间冲突的方法。 该方法包括为操作系统分配地址空间和用于监视器的地址空间。 该方法还包括将监视器的一部分映射到为操作系统分配的地址空间和为监视器分配的地址空间，以及将监视器的另一部分定位在为监视器分配的地址空间中。 该方法还包括检测操作系统尝试访问由分配给操作系统的地址空间内的监视器部分占据的区域，以及将该监视器的该部分重新定位在该地址空间内，以允许操作系统访问 以前由监视器的该部分占据的区域。

公开(公告)号：US20180146059A1

公开(公告)日：2018-05-24

申请号：US15414462

申请日：2017-01-24

申请人： Sebastian Schoenberg ,  Andrew Stephen Brown ,  Srikathyayani Srikanteswara ,  Jessica C. McCarthy ,  Eve M. Schooler ,  Christian Maciocco ,  Hassnaa Moustafa ,  Nageen Himayat ,  Rath Vannithamby ,  David John Zage

发明人： Sebastian Schoenberg ,  Andrew Stephen Brown ,  Srikathyayani Srikanteswara ,  Jessica C. McCarthy ,  Eve M. Schooler ,  Christian Maciocco ,  Hassnaa Moustafa ,  Nageen Himayat ,  Rath Vannithamby ,  David John Zage

IPC分类号： H04L29/08 ,  H04L12/24 ,  H04L12/26

摘要： Generally discussed herein are systems, devices, and methods for populating a cache in an information-centric network. A device of an ICN can include a content store including published content and attributes of the published content stored thereon, the attributes including at least two of a device from which the content originated attribute, a lineage attribute, and a service level agreement attribute, and content processing circuitry coupled to the content store, the content processing circuitry configured to manage the published content based on the attributes.

公开(公告)号：US08819699B2

公开(公告)日：2014-08-26

申请号：US11618446

申请日：2006-12-29

申请人： Erik C. Cota-Robles ,  Steven M. Bennett ,  Andrew V. Anderson ,  Sebastian Schoenberg

发明人： Erik C. Cota-Robles ,  Steven M. Bennett ,  Andrew V. Anderson ,  Sebastian Schoenberg

IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00

CPC分类号： G06F9/45558 ,  G06F2009/45566

摘要： Embodiments of apparatuses, methods, and systems for controlling virtual machines based on performance counters are disclosed. In one embodiment, an apparatus includes an event counter, a comparator, and virtualization control logic. The event counter is to keep an event count based on the number of occurrences of an event. The comparator is to determine whether the event count has reached a threshold value. The virtualization control logic is to transfer control of the apparatus from a guest to a host in response to the comparator determining that the event count has reached the threshold value.

摘要翻译： 公开了用于基于性能计数器来控制虚拟机的设备，方法和系统的实施例。 在一个实施例中，装置包括事件计数器，比较器和虚拟化控制逻辑。 事件计数器是根据事件的发生次数来保持事件计数。 比较器是确定事件计数是否达到阈值。 响应于比较器确定事件计数已经达到阈值，虚拟化控制逻辑是将设备从客户机的控制传送到主机。

公开(公告)号：US20140201421A1

公开(公告)日：2014-07-17

申请号：US13995126

申请日：2011-12-22

申请人： Sebastian Schoenberg

发明人： Sebastian Schoenberg

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F9/45558 ,  G06F12/1027 ,  G06F2009/45583 ,  G06F2212/681

摘要： Embodiments of systems, apparatuses, and methods for performing guest logical memory address to host physical memory address translation are described. In some embodiments, a system receives the guest logical memory address and determines an index page reference from the guest logical memory address. The system further retrieves a page index corresponding to the virtual machine. In addition, the system retrieves a first part of the host physical memory address from index page using the page index and a second part of the host physical memory address from the guest logical memory address. The system generates the host physical memory address from the first and second parts of the host physical memory address.

摘要翻译： 描述用于执行访客逻辑存储器地址以主机物理存储器地址转换的系统，装置和方法的实施例。 在一些实施例中，系统接收来宾逻辑存储器地址，并从来宾逻辑存储器地址确定索引页引用。 该系统进一步检索对应于虚拟机的页面索引。 此外，系统使用页面索引从索引页面检索主机物理内存地址的第一部分，并从客户机逻辑内存地址检索主机物理内存地址的第二部分。 系统从主机物理内存地址的第一和第二部分生成主机物理内存地址。

公开(公告)号：US20140096235A1

公开(公告)日：2014-04-03

申请号：US13630592

申请日：2012-09-28

申请人： Joshua Fryman ,  Nicholas Carter ,  Robert Knauerhase ,  Sebastian Schoenberg ,  Aditya Agrawal

发明人： Joshua Fryman ,  Nicholas Carter ,  Robert Knauerhase ,  Sebastian Schoenberg ,  Aditya Agrawal

IPC分类号： G06F12/14

CPC分类号： G06F12/14 ,  G06F12/00 ,  G06F12/1441 ,  G06F13/16 ,  G06F13/1668 ,  Y02D10/13 ,  Y02D10/14

摘要： A system implements dishonest policies for managing unauthorized access requests. The system includes memory management hardware to store a set of dishonest policy bits, each dishonest policy bit that is configured to a predetermined value indicating disallowed access for one of a set of memory ranges. When a processor receives an access request for a location in a memory range to which access is not allowed as indicated by a set dishonest policy bit, the processor returns a false indication according to a dishonest policy that the requested access has been performed.

摘要翻译： 系统实施不诚实的策略来管理未经授权的访问请求。 该系统包括用于存储一组不诚实的策略位的存储器管理硬件，每个不诚实的策略位被配置为指示一组存储器范围中的一个的不允许的访问的预定值。 当处理器接收到对于由设置的不诚实策略位指示的不允许访问的存储器范围内的位置的访问请求时，处理器根据执行请求的访问的不诚实的策略返回错误的指示。