公开(公告)号：US5862357A

公开(公告)日：1999-01-19

申请号：US674688

申请日：1996-07-02

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F15/16 ,  G06F12/06 ,  G06F15/173 ,  G06F13/00

CPC分类号： G06F12/0692 ,  G06F12/0284

摘要： A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

公开(公告)号：US06578071B2

公开(公告)日：2003-06-10

申请号：US09809938

申请日：2001-03-15

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F1300

CPC分类号： G06F12/0692 ,  G06F12/0284

摘要： A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

摘要翻译： 对称多处理系统包括通过分层总线互连的多个节点。 为了允许在节点之间传输数据并限制本地事务的全局传输，定义了多个地址分区：全局空间，本地空间，远程读取空间以及远程读写空间。 使用本地空间访问处理私有数据和本地数据。 使用全局空间访问全局数据。 在一个实施例中，操作系统的内核驻留在每个节点的本地空间中。 因为内核所在的内存空间被指定为本地空间，所以没有其他节点可以写入或损坏该节点的内核。

公开(公告)号：US5903907A

公开(公告)日：1999-05-11

申请号：US674560

申请日：1996-07-01

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F15/16 ,  G06F12/08

CPC分类号： G06F12/0811 ,  G06F2212/2542 ,  G06F2212/272

摘要： A flexible scheme is provided for designating the appropriate write-back protocol best suited for each memory level within a multi-level-cache computer system. The skip-level memory hierarchy of the present invention includes a lower-level copy-back cache and a higher-level write-through cache. This greatly simplifies the implementation of the higher-level cache, since it may be implemented with a write-or-read access to its address tag. Although counterintuitive, a write-through higher-level cache in a distributed shared memory may also increase the efficiency of the computer system without unduly increasing the volume of network traffic within the computer system. This is because a write-through higher-level cache increases the probability of readily-available cached copies of updated data which are consistent with the home copies of the data, thereby reducing the number of fetches from remote home locations whenever the data is not found in the lower-level cache but is found in the higher-level cache.

摘要翻译： 提供了一种灵活的方案，用于指定最适合多级缓存计算机系统内的每个存储器级别的适当的回写协议。 本发明的跳过级存储器层次结构包括下级复制高速缓存和较高级别的直写高速缓存。 这大大简化了高级缓存的实现，因为它可以通过对其地址标签的写或读访问来实现。 尽管是直观的，但分布式共享存储器中的直写式更高级缓存也可以提高计算机系统的效率，而不会不适当地增加计算机系统内的网络流量。 这是因为直写高级缓存增加了与数据的归属副本一致的更新数据的易于获得的高速缓存副本的概率，从而在没有找到数据时减少从远程归属位置获取的数量 在较低级缓存中，但在较高级缓存中找到。

公开(公告)号：US5802563A

公开(公告)日：1998-09-01

申请号：US674029

申请日：1996-07-01

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0888 ,  G06F2212/2542 ,  G06F2212/272

摘要： Memory space in the lower-level cache (LLC) of a computer system is allocated in cache-line sized units, while memory space in the higher-level cache (HLC) of the computer system is allocated in page sized units; with each page including two or more cache lines. Accordingly, during the execution of a program, cache-line-sized components of a page-sized block of data are incrementally stored in the cache lines of the LLCs. Subsequently, the system determines that it is time to review the allocation of cache resources, i.e., between the LLC and the HLC. The review trigger may be external to the processor, e.g., a timer interrupting the processor on a periodic basis. Alternatively, the review trigger may be from the LLC or the HLC, e.g., when the LLC is full, or when usage of the HLC drops below a certain percentage. A review of the allocation involves identifying components associated with their respective blocks of data and determining if the number of cached components identified with the blocks exceed a threshold. If the threshold is exceeded for cached components associated with a particular block, space is allocated in the HLC for storing components from the block. This scheme advantageously increases the likelihood of future cache hits by optimally using the HLC to store blocks of memory with a substantial number of uses components.

摘要翻译： 计算机系统的低级缓存（LLC）中的存储器空间被分配在高速缓存行大小的单元中，而计​​算机系统的高级缓存（HLC）中的存储器空间被分配为页大小的单元; 每个页面包括两个或多个缓存行。 因此，在执行程序期间，页面大小的数据块的高速缓存行大小的组件被递增地存储在LLC的高速缓存行中。 随后，系统确定是时候审查高速缓存资源的分配，即在LLC和HLC之间。 审查触发可以在处理器的外部，例如定时器周期性地中断处理器。 或者，审查触发可以来自LLC或HLC，例如当LLC已满时，或者当HLC的使用下降到特定百分比以下时。 对分配的审查包括识别与其相应数据块相关联的组件，并确定用块识别的高速缓存组件的数量是否超过阈值。 如果超过与特定块相关联的缓存组件的阈值，则在HLC中分配空间以从块中存储组件。 该方案有利地通过最佳地使用HLC来存储具有相当数量的使用组件的存储块来增加未来高速缓存命中的可能性。

公开(公告)号：US5734922A

公开(公告)日：1998-03-31

申请号：US674330

申请日：1996-07-01

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F12/08 ,  G06F15/16 ,  G06F15/177 ,  G06F12/04 ,  G06F13/16

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F2212/272

摘要： A computer system includes a directory at each node which stores coherency information for the coherency units for which that node is the home node. In addition, the directory stores a data access state corresponding to each coherency unit which indicates the data access pattern observed for that coherency unit. The data access state may indicate migratory or non-migratory data access patterns. If the coherency unit has been observed to have a migratory data access pattern, then read/write access rights are granted. Conversely, if the coherency unit has been observed to have non-migratory data access patterns, then read access rights are granted. The home node further detects the migratory and non-migratory data access patterns and selects transitions between the migratory and non-migratory data access states independent of the cache hierarchies within the nodes which access the affected coherency unit. In one embodiment, a pair of counters are employed for each coherency unit. One of the counters is incremented when the coherency unit is in the migratory data access state and a data migration is detected. The other counter is incremented when the coherency unit is in the non-migratory data access state and a data migration is detected. When one of the counters overflows, the home node transitions the data access state of the coherency unit to the alternate data access state.

摘要翻译： 计算机系统包括在每个节点处的目录，其存储该节点是家庭节点的一致性单元的一致性信息。 此外，目录存储对应于每个相关性单元的数据访问状态，其指示为该相关性单元观察到的数据访问模式。 数据访问状态可以指示迁移或非迁移数据访问模式。 如果观察到一致性单元具有迁移数据访问模式，则授予读/写访问权限。 相反，如果已经观察到相关性单元具有非迁移性数据访问模式，则授予读访问权限。 归属节点还检测迁移和非迁移数据访问模式，并选择迁移和非迁移数据访问状态之间的转换，而不依赖于访问受影响的一致性单元的节点内的高速缓存层次。 在一个实施例中，对于每个相干单元采用一对计数器。 当一致性单元处于迁移数据访问状态并检测到数据迁移时，其中一个计数器递增。 当一致性单元处于非迁移数据访问状态并检测到数据迁移时，另一个计数器递增。 当其中一个计数器溢出时，主节点将一致性单元的数据访问状态转换到备用数据访问状态。

公开(公告)号：US06826660B2

公开(公告)日：2004-11-30

申请号：US10073712

申请日：2002-02-11

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F1200

CPC分类号： G06F12/0692 ,  G06F12/0284

摘要： A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node.

摘要翻译： 对称多处理系统包括通过分层总线互连的多个节点。 为了允许在节点之间传输数据并限制本地事务的全局传输，定义了多个地址分区：全局空间，本地空间，远程读取空间以及远程读写空间。 使用本地空间访问处理私有数据和本地数据。 使用全局空间访问全局数据。 在一个实施例中，操作系统的内核驻留在每个节点的本地空间中。

公开(公告)号：US06654866B2

公开(公告)日：2003-11-25

申请号：US09940172

申请日：2001-08-27

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F1210

CPC分类号： G06F11/0712 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0766 ,  G06F12/0284 ,  G06F12/0864 ,  G06F12/1018 ,  G06F12/1072 ,  G06F2212/2542 ,  G06F2212/272

摘要： A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copied to local memory space of a node such that accesses to the data may be performed locally rather than globally. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, multiple pages of the address space are mapped to an entry in a translation table. To decrease the probability that an entry is not available for a page, the translation table may be implemented as a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

公开(公告)号：US5893150A

公开(公告)日：1999-04-06

申请号：US675306

申请日：1996-07-01

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0888 ,  G06F12/0813

摘要： An efficient cache allocation scheme is provided for both uniprocessor and multiprocessor computer systems having at least one cache. In one embodiment, upon the detection of a cache miss, a determination of whether the cache miss is "avoidable" is made. In other words, would the present cache miss have occurred if the data had been cached previously and if the data had remained in the cache. One example of an avoidable cache miss in a multiprocessor system having a distributed memory architecture is an excess cache miss. An excess cache miss is either a capacity miss or a conflict miss. A capacity miss is caused by the insufficient size of the cache. A conflict miss is caused by insufficient depth in the associativity of the cache. The determination of the excess cache miss involves tracking read and write requests for data by the various processors and storing some record of the read/write request history in a table or linked list. Data is cached only after an avoidable cache miss has occurred. By caching only after at least one avoidable cache miss instead of upon every (initial) access, cache space can be allocated in a highly efficient manner thereby minimizing the number of data fetches caused by cache misses.

摘要翻译： 为具有至少一个高速缓存的单处理器和多处理器计算机系统提供有效的高速缓存分配方案。 在一个实施例中，当检测到高速缓存未命中时，确定高速缓存未命中是否“可避免”。 换句话说，如果先前缓存了数据，并且数据保留在高速缓存中，现在的高速缓存未命中是否发生。 具有分布式存储器架构的多处理器系统中的可避免的高速缓存未命中的一个示例是多余的高速缓存未命中。 多余的高速缓存未命中是容量错误或冲突错过。 容量丢失是由缓存大小不足引起的。 冲突错过是由缓存的关联性不够深造成的。 多余缓存未命中的确定包括跟踪各种处理器对数据的读和写请求，并将读/写请求历史的一些记录存储在表或链表中。 仅在发生可避免的缓存未命中之后才会缓存数据。 通过仅在至少一个可避免的缓存未命中而不是每次（初始）访问之后进行缓存，可以高效地分配高速缓存空间，从而最小化由高速缓存未命中引起的数据获取的数量。

公开(公告)号：US06308246B1

公开(公告)日：2001-10-23

申请号：US09148820

申请日：1998-09-04

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F1210

CPC分类号： G06F11/0712 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0766 ,  G06F12/0284 ,  G06F12/0864 ,  G06F12/1018 ,  G06F12/1072 ,  G06F2212/2542 ,  G06F2212/272

摘要： A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copies to local memory space of a node such that accesses to the data may be performed locally rather than globally. The copies data is referred to as a shadow page. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, the page to which shadow copies may be stored and which global addresses may be converted to local physical addresses may be restricted. Multiple page of local memory space may be allocated to one entry of a local physical address to global address (LPA2GA) table. When a page is allocated to store shadow pages, an entry in the LPA2GA table associated with that page is marked as unavailable. Accordingly, new translations may not be stored to that entry of the LPA2GA table and other pages associated with that entry may not be allocated to store shadow pages. In a similar manner, multiple pages of the global address space are mapped to an entry in a global address to local physical address(GA2LPA) translation table. When data corresponding to a page within the global address space is stored as a shadow page, the entry associated with the global address is marked as unavailable. Accordingly, other pages associated with that entry of the GA2LPA table may not be stored as shadow pages because the entry is not available. The local copy of the data is not stored and the node must access the data globally. To decrease the probability that an entry is not available for a page, the GA2LPA table may be implemented as a set associative table. To further increase the availability of entries in the GA2LPA table, a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

公开(公告)号：US06226671B1

公开(公告)日：2001-05-01

申请号：US09126053

申请日：1998-07-30

申请人： Erik E. Hagersten ,  Mark D. Hill

发明人： Erik E. Hagersten ,  Mark D. Hill

IPC分类号： G06F1300

CPC分类号： G06F12/0692 ,  G06F12/0284

摘要： A shared memory system for symmetric multiprocessing systems including a plurality of physical memory locations in which the locations are either allocated to one node of a plurality of processing nodes, equally distributed among the processing nodes, or unequally distributed among the processing nodes. The memory locations are configured to be accessed by the plurality of processing nodes by mapping all memory locations into a plurality of address partitions within a hierarchy bus. The memory locations are addressed by a plurality of address aliases within the bus while the properties of the address partitions are employed to control transaction access generated in the processing nodes to memory locations allocated locally and globally within the processing nodes.

摘要翻译： 一种用于对称多处理系统的共享存储器系统，包括多个物理存储器位置，其中位置被分配给多个处理节点中的一个节点，在处理节点之间分布均匀，或者在处理节点之间不等分布。 通过将所有存储器位置映射到层次总线内的多个地址分区中，存储器位置被配置为被多个处理节点访问。 存储器位置由总线内的多个地址别名来寻址，同时使用地址分区的属性来控制处理节点中生成的事务访问到处理节点内本地和全局分配的存储器位置。