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1.发明授权公开(公告)号：US07817719B2
公开(公告)日：2010-10-19
申请号：US11140749
申请日：2005-05-31
申请人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
摘要： An adaptation of the sum-of-absolute-differences (SAD) calculation is implemented by modifying existing circuitry in a microprocessor. The adaptation yields a reduction of over 30% for a current SAD calculation. The adaptation includes a first and second operand register, each storing respectively a first and second set of 2's complement binary data, an arithmetic logic unit (ALU), and a destination register. An add/subtract enable input on the ALU receives a most significant bit (MSB) of the second set of binary data. The ALU adds the first and second data sets if the MSB is a “0” and subtracts the second data set from the first data set if the MSB is a “1.” The add/subtract enable input has the effect of taking the absolute value of the second data set without having to first perform an absolute value determination, thus eliminating processing steps.
摘要翻译： 通过修改微处理器中的现有电路来实现绝对差值（SAD）计算的适应。 对于当前的SAD计算，适应性减少超过30％。 适配包括第一和第二操作数寄存器，每个寄存器分别存储第二和第二组二进制补码二进制数据，算术逻辑单元（ALU）和目的地寄存器。 ALU上的加/减使能输入接收第二组二进制数据的最高有效位（MSB）。 如果MSB为“0”，则ALU将第一和第二数据组相加，如果MSB为“1”，则从第一数据组中减去第二数据组。加/减使能输入具有采用绝对值 值，而不必首先执行绝对值确定，从而消除处理步骤。
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公开(公告)号：US20090265410A1
公开(公告)日：2009-10-22
申请号：US12494022
申请日：2009-06-29
申请人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
CPC分类号： G06F7/505 , G06F7/49921 , G06F9/30014 , G06F9/30036 , G06F9/3885 , G06F17/142 , G06F2207/382
摘要： A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.
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3.发明申请METHODS AND PROCESSOR-RELATED MEDIA TO PERFORM RAPID RETURNS FROM SUBROUTINES IN MICROPROCESSORS AND MICROCONTROLLERS 有权方法和处理器相关的介质，用于在微波处理器和微控制器中从SUBROUTINES执行快速返回公开(公告)号：US20100250904A1
公开(公告)日：2010-09-30
申请号：US12795582
申请日：2010-06-07
申请人： Erik K. Renno , Oyvind Strom , Morten W. Lund
发明人： Erik K. Renno , Oyvind Strom , Morten W. Lund
IPC分类号： G06F9/318
CPC分类号： G06F9/30072 , G06F9/30054 , G06F9/30094 , G06F9/3806
摘要： Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single instruction.
摘要翻译： 各种实施例包括用于执行包括返回操作的操作的方法和相关介质。 一种这样的方法包括测试返回值寄存器的内容和设置状态标志。 测试返回值寄存器的内容并设置状态标志是响应于单个指令执行的。
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公开(公告)号：US07555514B2
公开(公告)日：2009-06-30
申请号：US11352711
申请日：2006-02-13
申请人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
IPC分类号： G06F7/50
CPC分类号： G06F7/505 , G06F7/49921 , G06F9/30014 , G06F9/30036 , G06F9/3885 , G06F17/142 , G06F2207/382
摘要： A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.
摘要翻译： 一个微处理器的加字和减法操作由微处理器并行地由从寄存器文件的指定的源寄存器的指定的顶部或底部的半字位置获得的半字操作数并行，并且这些操作的和和差分结果被打包 分配到指定目的地寄存器的相应顶部和底部半字位置。 微处理器包括具有加法器电路的加法器电路的算术逻辑单元（ALU），其可选择性地分成独立的可选择的半字加法器，以对所选择的半字操作数执行加法运算或减法运算。 ALU的半字加法器通过一组多路复用器从源寄存器访问操作数，这些复用器在顶部和底部的半字位置之间进行选择。 还可以提供对和差和差异结果的减半和饱和度修改的操作。
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公开(公告)号：US20120036299A1
公开(公告)日：2012-02-09
申请号：US13267933
申请日：2011-10-07
申请人： Erik K. Renno
发明人： Erik K. Renno
CPC分类号： G06F21/79 , G06F12/1433
摘要： Apparatus, systems, and methods may operate to receive from a requesting device, at a memory device, a request to access a memory domain associated with the memory device, and to deny, by the memory device, the request if the memory domain comprises any part of a secure domain, and the requesting device has not asserted a secure transfer indication. Additional operations may include granting the request if the memory domain comprises some part of the secure domain and the requesting device has asserted the secure transfer signal, or if the memory domain comprises only a non-secure domain. Additional apparatus, systems, and methods are disclosed.
摘要翻译： 设备，系统和方法可以操作以在存储器设备处从请求设备接收访问与存储器设备相关联的存储器域的请求，并且由存储器设备拒绝该请求，如果存储器域包括任何 安全域的一部分，并且请求设备尚未确定安全传输指示。 附加操作可以包括如果存储器域包括安全域的某些部分并且请求设备已经确定了安全传输信号，或者如果存储器域仅包括非安全域，则授予请求。 公开了附加装置，系统和方法。
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6.发明授权Microprocessor instruction that allows system routine calls and returns from all contexts 有权允许系统例程调用和从所有上下文返回的微处理器指令公开(公告)号：US07996659B2
公开(公告)日：2011-08-09
申请号：US11145613
申请日：2005-06-06
IPC分类号： G06F9/00
CPC分类号： G06F9/30181 , G06F9/30101 , G06F9/4486
摘要： An apparatus comprises register means for storing a return context upon initiation of a supervisor call instruction and restoring means to restore a privilege level and status register upon execution of a supervisor return instruction. The supervisor call instruction can be called from all contexts.
摘要翻译： 一种装置，包括：登记装置，用于在启动监督程序调用指令时存储返回上下文;以及恢复装置，用于在执行管理程序返回指令时恢复特权级别和状态寄存器。 可以从所有上下文调用主管调用指令。
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7.发明授权Microprocessor access of operand stack as a register file using native instructions 有权使用本地指令将操作数堆栈的微处理器访问作为寄存器文件公开(公告)号：US07478224B2
公开(公告)日：2009-01-13
申请号：US11107235
申请日：2005-04-15
申请人： Oyvind Strom , Erik K. Renno , Kristian Monsen
发明人： Oyvind Strom , Erik K. Renno , Kristian Monsen
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/3016 , G06F9/30196 , G06F9/321 , G06F9/3861
摘要： A combined native (RISC or CISC) microprocessor and stack (Java™) machine are constructed so that Java™ VM instructions can be executed in hardware. Most Java™ instructions are executed directly, while more complex Java™ instructions, such as those manipulating Java™ objects, are executed as native microcode. In order for native microcode instructions to access the Java™ operand stack, a Java™ operand stack pointer points to the register file location that is the current top of the stack, while a remap bit in the status register indicates that registers specified in native instructions are remapped as the maximum Java™ operand stack pointer value minus the present value of the Java™ operand stack pointer.
摘要翻译： 构建了本机（RISC或CISC）微处理器和堆栈（Java（TM））机器，以便Java（TM）VM指令可以在硬件中执行。 大多数Java（TM）指令都是直接执行的，而诸如操作Java（TM）对象的那些更复杂的Java TM指令被执行为本地微代码。 为了使本地微代码指令访问Java（TM）操作数堆栈，Java（TM）操作数堆栈指针指向作为堆栈当前顶部的寄存器文件位置，而状态寄存器中的重映射位指示寄存器 在本地指令中指定的内容将重新映射为最大Java（TM）操作数堆栈指针值减去Java（TM）操作数堆栈指针的当前值。
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公开(公告)号：US07243210B2
公开(公告)日：2007-07-10
申请号：US11140750
申请日：2005-05-31
申请人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
IPC分类号： G06F12/06
CPC分类号： G06F9/355 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A multiplexer has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control passes the specified byte to its output. The extracted byte is provided directly at specific bit positions of a zero-extended address offset word. The offset word is added to the base address, the sum being used to address memory contents that are loaded into the destination register.
摘要翻译： 可用于可寻址寻址存储器的索引寻址的微处理器电路包括由指令指定的字长索引，基地址和目标寄存器。 该指令还指定要提取的索引寄存器中打包的一个字节。 多路复用器具有访问索引寄存器的所有字节的字宽输入端，并且响应于字节选择控制将指定的字节传递到其输出。 提取的字节直接在零扩展地址偏移字的特定位位置处提供。 偏移字被添加到基址中，该和用于寻址加载到目标寄存器中的存储器内容。
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9.发明授权Method for performing a return operation in parallel with setting status flags based on a return value register test 有权基于返回值寄存器测试与设置状态标志并行执行返回操作的方法公开(公告)号：US08555041B2
公开(公告)日：2013-10-08
申请号：US12795582
申请日：2010-06-07
申请人： Erik K. Renno , Oyvind Strom , Morten W. Lund
发明人： Erik K. Renno , Oyvind Strom , Morten W. Lund
IPC分类号： G06F9/00
CPC分类号： G06F9/30072 , G06F9/30054 , G06F9/30094 , G06F9/3806
摘要： Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting status flags. Testing the content of the return value register and setting the status flags are performed in response to a single instruction.
摘要翻译： 各种实施例包括用于执行包括返回操作的操作的方法和相关介质。 一种这样的方法包括测试返回值寄存器的内容和设置状态标志。 测试返回值寄存器的内容并设置状态标志是响应于单个指令执行的。
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公开(公告)号：US08224883B2
公开(公告)日：2012-07-17
申请号：US12494022
申请日：2009-06-29
申请人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
发明人： Ronny Pedersen , Erik K. Renno , Oyvind Strom
CPC分类号： G06F7/505 , G06F7/49921 , G06F9/30014 , G06F9/30036 , G06F9/3885 , G06F17/142 , G06F2207/382
摘要： A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided.
摘要翻译： 一个微处理器的加字和减法操作由微处理器并行地由从寄存器文件的指定的源寄存器的指定的顶部或底部的半字位置获得的半字操作数并行，并且这些操作的和和差分结果被打包 分配到指定目的地寄存器的相应顶部和底部半字位置。 微处理器包括具有加法器电路的加法器电路的算术逻辑单元（ALU），其可选择性地分成独立的可选择的半字加法器，以对所选择的半字操作数执行加法运算或减法运算。 ALU的半字加法器通过一组多路复用器从源寄存器访问操作数，这些复用器在顶部和底部的半字位置之间进行选择。 还可以提供对和差和差异结果的减半和饱和度修改的操作。
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