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公开(公告)号：US20120023317A1
公开(公告)日：2012-01-26
申请号：US13187413
申请日：2011-07-20
申请人： Erkut UYGUN , Jan Guffens , Paul Tindall
发明人： Erkut UYGUN , Jan Guffens , Paul Tindall
IPC分类号： G06F9/30
CPC分类号： G06F8/34
摘要： A digital data processing system that is designed to facilitate use of UML activity diagrams.
摘要翻译： 一种数字数据处理系统，旨在便于使用UML活动图。
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公开(公告)号：US09507569B2
公开(公告)日：2016-11-29
申请号：US13187413
申请日：2011-07-20
申请人： Erkut Uygun , Jan Guffens , Paul Tindall
发明人： Erkut Uygun , Jan Guffens , Paul Tindall
IPC分类号： G06F9/44
CPC分类号： G06F8/34
摘要： A digital data processing system that is designed to facilitate use of UML activity diagrams.
摘要翻译： 一种数字数据处理系统，旨在便于使用UML活动图。
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公开(公告)号：US07689735B2
公开(公告)日：2010-03-30
申请号：US11240637
申请日：2005-10-03
CPC分类号： G06F9/3802
摘要： An interface requests instructions from a data store storing instructions of an application to be processed by a data processor, and receives and transmits the instructions to the data processor. The interface includes: an input that receives the instructions from the data store via at least one input bus; a buffer that stores received instructions; an output that outputs instructions to the data processing apparatus via the output bus; a control signal input that receives a control signal; and a buffer controller that controls the buffer to request an instruction subsequent to a previously received instruction within an instruction stream of the application from the data store in response to detection of no control signal on the control signal input and to detection of available buffer storage capacity. In response to a control signal received at the control signal input, the controller controls at least one of input and storage of instructions within the interface in order to seek to reduce instruction movement through the input.
摘要翻译： 一个接口从存储由数据处理器处理的应用的指令的数据存储器请求指令，并且接收并发送指令给数据处理器。 接口包括：经由至少一个输入总线从数据存储器接收指令的输入; 存储接收到的指令的缓冲区; 经由输出总线向数据处理装置输出指令的输出; 接收控制信号的控制信号输入; 以及缓冲器控制器，其响应于在控制信号输入上没有控制信号的检测和控制信号输入的检测，控制缓冲器从数据存储器请求在应用的指令流之内的先前接收到的指令之后的指令， 。 响应于在控制信号输入处接收到的控制信号，控制器控制接口内的指令的输入和存储中的至少一个，以便寻求减少通过输入的指令移动。
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4.发明授权公开(公告)号：US06588009B1
公开(公告)日：2003-07-01
申请号：US09450325
申请日：1999-11-29
申请人： Jan Guffens , Kurt Du Pont
发明人： Jan Guffens , Kurt Du Pont
IPC分类号： G06F945
摘要： A method and apparatus for optimizing the compilation of a computer program by exposing parallelism are disclosed. Information describing the operations in the program and their sequence is extracted and stored in a data structure. The operations in the program which involve index expressions are identified and symbolically executed, producing information describing the memory accesses by the program. Operations which can be executed in parallel are identified based on the information describing memory accesses. The program is interrogated with questions in a question data structure relating to how the program accesses memory. The answers to the questions are accumulated in index sets and back annotated into the question data structure.
摘要翻译： 公开了一种通过暴露平行度优化计算机程序编译的方法和装置。 描述程序及其序列中的操作的信息被提取并存储在数据结构中。 识别并符号地执行涉及索引表达式的程序中的操作，产生描述程序的存储器访问的信息。 可以基于描述存储器访问的信息来识别可并行执行的操作。 询问有关程序访问内存的问题数据结构中的问题的程序。 这些问题的答案在索引集中累积，并将其注释到问题数据结构中。
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5.发明授权System for processing VLIW words containing variable length instructions having embedded instruction length identifiers 有权用于处理包含具有嵌入指令长度标识符的可变长度指令的VLIW字的系统公开(公告)号：US07302552B2
公开(公告)日：2007-11-27
申请号：US10963722
申请日：2004-10-14
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30101 , G06F9/3885
摘要： A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.
摘要翻译： 描述了包括独立地并行执行不同数据处理操作的多个数据路径元件的处理器。 提供了被编码的程序指令，以产生用于控制数据路径元件的控制信号。 支持相同数据处理操作的多个指令集，该数据处理操作将由不同指令集的不同指令内的相同数据路径元素进行不同编码。 这可以实现代码压缩，当可以实现很少的并行性并且在可能时指定完全并行性。
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公开(公告)号：US20050257028A1
公开(公告)日：2005-11-17
申请号：US10963722
申请日：2004-10-14
CPC分类号： G06F9/3853 , G06F9/30101 , G06F9/3885
摘要： A processor is described including a plurality of data path elements 2, 4, 6, 8 which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements. Multiple instruction sets are supported with the same data processing operation to be performed by the same data path element being differently encoded within different instructions of different instruction sets. This enables code compaction when little parallelism may be achieved and full parallelism to be specified when this is possible.
摘要翻译： 描述了处理器，其包括独立地并行执行不同数据处理操作的多个数据路径元件2,4,6,8。 提供了被编码的程序指令，以产生用于控制数据路径元件的控制信号。 支持相同数据处理操作的多个指令集，该数据处理操作将由不同指令集的不同指令内的相同数据路径元素进行不同编码。 这可以实现代码压缩，当可以实现很少的并行性并且在可能时指定完全并行性。
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公开(公告)号：US09858169B2
公开(公告)日：2018-01-02
申请号：US12458287
申请日：2009-07-07
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F11/3471 , G06F2201/86 , G06F2201/88
摘要： A data processing apparatus is disclosed that comprises monitoring circuitry for monitoring accesses to a plurality of addressable locations within said data processing apparatus that occur between start and end events said monitoring circuitry comprising: an address location store for storing data identifying said plurality of addressable locations to be monitored and a monitoring data store; said monitoring circuitry being responsive to detection of said start event to detect accesses to said plurality of addressable locations and to store monitoring data relating to a summary of said detected accesses in said monitoring data store; and said monitoring circuitry being responsive to detection of said end event to stop collecting said monitoring data; said monitoring circuit being responsive to detection of a flush event to output said stored monitoring data and to flush said monitoring data store.
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8.发明申请公开(公告)号：US20100077143A1
公开(公告)日：2010-03-25
申请号：US12458287
申请日：2009-07-07
CPC分类号： G06F11/348 , G06F11/3471 , G06F2201/86 , G06F2201/88
摘要： A data processing apparatus is disclosed that comprises monitoring circuitry for monitoring accesses to a plurality of addressable locations within said data processing apparatus that occur between start and end events said monitoring circuitry comprising: an address location store for storing data identifying said plurality of addressable locations to be monitored and a monitoring data store; said monitoring circuitry being responsive to detection of said start event to detect accesses to said plurality of addressable locations and to store monitoring data relating to a summary of said detected accesses in said monitoring data store; and said monitoring circuitry being responsive to detection of said end event to stop collecting said monitoring data; said monitoring circuit being responsive to detection of a flush event to output said stored monitoring data and to flush said monitoring data store.
摘要翻译： 公开了一种数据处理装置，其包括监视电路，用于监视对在所述数据处理装置内的多个可寻址位置的访问，所述数据处理装置在开始和结束事件之间发生，所述监视电路包括：地址位置存储器，用于存储识别所述多个可寻址位置的数据 监控和监控数据存储; 所述监视电路响应于所述起始事件的检测，以检测对所述多个可寻址位置的访问，并且存储与所述监视数据存储器中的所述检测到的访问的摘要相关的监视数据; 并且所述监视电路响应于所述结束事件的检测来停止收集所述监视数据; 所述监控电路响应于检测到刷新事件以输出所述存储的监视数据并刷新所述监视数据存储。
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公开(公告)号：US20070079110A1
公开(公告)日：2007-04-05
申请号：US11240637
申请日：2005-10-03
IPC分类号： G06F9/40
CPC分类号： G06F9/3802
摘要： An interface operable to request instructions from a data store storing instructions of an application to be processed by a data processor, and operable to receive and transmit said instructions to said data processor, said interface comprising: an input operable to receive said instructions from said data store via at least one input bus; a buffer operable to store said received instructions; an output operable to output said instructions to said data processing apparatus via at least one output bus; a control signal input operable to receive a control signal; and a buffer controller operable to: control said buffer to request an instruction subsequent to a previously received instruction within an instruction stream of said application from said data store in response to detection of no control signal on said control signal input and to detection of available buffer storage capacity; and in response to a control signal received at said control signal input, said controller is operable to control at least one of input and storage of instructions within said interface in order to seek to reduce instruction movement through said input.
摘要翻译： 一种可操作以从存储由数据处理器处理的应用的指令的数据存储器请求指令的接口，并且可操作以从所述数据处理器接收和发送所述指令，所述接口包括：可操作以从所述数据接收所述指令的输入 通过至少一个输入总线存储; 缓冲器，用于存储所述接收到的指令; 输出，用于经由至少一个输出总线将所述指令输出到所述数据处理装置; 控制信号输入，用于接收控制信号; 以及缓冲器控制器，其可操作用于：响应于所述控制信号输入上没有控制信号的检测和所述控制信号输入的检测，控制所述缓冲器以从所述数据存储器请求在所述应用的指令流之内的先前接收到的指令之后的指令 存储容量; 并且响应于在所述控制信号输入处接收到的控制信号，所述控制器可操作以控制所述接口内的指令的输入和存储中的至少一个，以便寻求减少通过所述输入的指令移动。
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10.发明授权公开(公告)号：US06539543B1
公开(公告)日：2003-03-25
申请号：US09450329
申请日：1999-11-29
申请人： Jan Guffens , Kurt Du Pont
发明人： Jan Guffens , Kurt Du Pont
IPC分类号： G06F945
摘要： A method and apparatus for optimizing the compilation of computer program by exposing parallelism are disclosed. The computer program contains steps which involve index expressions. The program also involves function calls. An index path in the program is identified by noting the steps involving index expressions. A non-hierarchical representation of the index path, including operations in the function calls is created and interrogated with questions relating to memory accesses. The results of the interrogation are stored in or back annotated to a question data structure. The method and apparatus preferably involve the use of a signal flow graph which is completed using the information in the question data structure.
摘要翻译： 公开了一种通过暴露平行度优化计算机程序编译的方法和装置。 计算机程序包含涉及索引表达式的步骤。 该程序还涉及到函数调用。 通过注意涉及索引表达式的步骤来识别程序中的索引路径。 创建索引路径的非分层表示，包括函数调用中的操作，并询问与存储器访问有关的问题。 询问的结果存储在问题数据结构中或后面注解为问题数据结构。 该方法和装置优选地涉及使用在问题数据结构中使用信息完成的信号流图。
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