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    Microstrip line structures with alternating wide and narrow portions having different thicknesses relative to ground, method of manufacture and design structures
    2.
    发明授权
    Microstrip line structures with alternating wide and narrow portions having different thicknesses relative to ground, method of manufacture and design structures 有权
    具有相对于地面具有不同厚度的交替宽和窄部分的微带线结构，制造方法和设计结构

    公开(公告)号：US08766748B2

    公开(公告)日：2014-07-01

    申请号：US12960009

    申请日：2010-12-03

    申请人： Essam Mina ,  Guoan Wang ,  Wayne H. Woods, Jr.

    发明人： Essam Mina ,  Guoan Wang ,  Wayne H. Woods, Jr.

    IPC分类号： H01P3/08 ,  H01P9/00

    CPC分类号： H01P3/081 ,  H01P3/003 ,  H01P9/00

    摘要： On-chip high performance slow-wave microstrip line structures, methods of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a different plane than the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness such that a height of the wide portion is different than a height of the narrow portion with respect to the at least one ground.

    摘要翻译： 本文提供片上高性能慢波微带线结构，集成电路的制造方法和设计结构。 该结构包括设置在与至少一个地面不同的平面中的至少一个地面和信号层。 信号层具有至少一个交替宽的部分和具有交替厚度的窄部分，使得宽部分的高度不同于窄部分相对于至少一个地面的高度。

    ON-CHIP HIGH PERFORMANCE SLOW-WAVE MICROSTRIP LINE STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
    3.
    发明申请
    ON-CHIP HIGH PERFORMANCE SLOW-WAVE MICROSTRIP LINE STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
    片上高性能慢波微波线结构，制造方法和设计结构

    公开(公告)号：US20120139668A1

    公开(公告)日：2012-06-07

    申请号：US12960009

    申请日：2010-12-03

    申请人： Essam MINA ,  Guoan Wang ,  Wayne H. Woods, JR.

    发明人： Essam MINA ,  Guoan Wang ,  Wayne H. Woods, JR.

    IPC分类号： H01P3/08

    CPC分类号： H01P3/081 ,  H01P3/003 ,  H01P9/00

    摘要： On-chip high performance slow-wave microstrip line structures, methods of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a different plane than the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness such that a height of the wide portion is different than a height of the narrow portion with respect to the at least one ground.

    摘要翻译： 本文提供片上高性能慢波微带线结构，集成电路的制造方法和设计结构。 该结构包括设置在与至少一个地面不同的平面中的至少一个地面和信号层。 信号层具有至少一个交替宽的部分和具有交替厚度的窄部分，使得宽部分的高度不同于窄部分相对于至少一个地面的高度。

    ON-CHIP HIGH PERFORMANCE SLOW-WAVE COPLANAR WAVEGUIDE STRUCTURES, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
    4.
    发明申请
    ON-CHIP HIGH PERFORMANCE SLOW-WAVE COPLANAR WAVEGUIDE STRUCTURES, METHOD OF MANUFACTURE AND DESIGN STRUCTURE 失效
    片上高性能慢波共晶波形结构，制造方法和设计结构

    公开(公告)号：US20120139667A1

    公开(公告)日：2012-06-07

    申请号：US12959997

    申请日：2010-12-03

    申请人： Essam MINA ,  Guoan Wang ,  Wayne H. Woods, JR.

    发明人： Essam MINA ,  Guoan Wang ,  Wayne H. Woods, JR.

    IPC分类号： H01P3/08

    CPC分类号： H01P3/081 ,  H01P3/003 ,  H01P9/00

    摘要： On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness. The wide portion extends toward the at least one ground.

    摘要翻译： 本文提供片上高性能慢波共面波导结构，集成电路的制造方法和设计结构。 该结构包括设置在与至少一个地面相同的平面中的至少一个接地和信号层。 信号层具有至少一个交替宽的部分和具有交替厚度的窄部分。 宽部分朝向至少一个地面延伸。

    Compact On-Chip Branchline Coupler Using Slow Wave Transmission Line
    5.
    发明申请
    Compact On-Chip Branchline Coupler Using Slow Wave Transmission Line 有权
    使用慢波传输线的紧凑型片上分支线耦合器

    公开(公告)号：US20110043299A1

    公开(公告)日：2011-02-24

    申请号：US12542958

    申请日：2009-08-18

    申请人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne H. Woods, JR.

    发明人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne H. Woods, JR.

    IPC分类号： H01P5/18 ,  H01P1/18

    CPC分类号： H01P3/082 ,  H01L27/0617 ,  H01L27/0629 ,  H01P5/227

    摘要： Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.

    摘要翻译： 使用慢波传输线效应的分支线耦合器结构具有每单位长度的大电感和大电容。 支线耦合器结构包括多个四分之一波长传输线，其中至少一个包括高阻抗臂和低阻抗臂。 高阻抗和低阻抗是相对的。 高阻抗臂包括多个窄电池并且具有nL的电感和C / n的电容，并且低阻抗臂包括多个宽电池并且具有L / n的电感和nC的电容。 宽和窄的单元彼此相对，并且宽和窄的单元彼此相邻以形成具有阶梯不连续替代宽度的信号层。

    Compact on-chip branchline coupler using slow wave transmission line
    7.
    发明授权
    Compact on-chip branchline coupler using slow wave transmission line 有权
    使用慢波传输线的紧凑型片上分支线耦合器

    公开(公告)号：US08188808B2

    公开(公告)日：2012-05-29

    申请号：US12542958

    申请日：2009-08-18

    申请人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne H. Woods, Jr.

    发明人： Hanyi Ding ,  Essam Mina ,  Guoan Wang ,  Wayne H. Woods, Jr.

    IPC分类号： H01P5/18 ,  H01P9/00

    CPC分类号： H01P3/082 ,  H01L27/0617 ,  H01L27/0629 ,  H01P5/227

    摘要： Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.

    摘要翻译： 使用慢波传输线效应的分支线耦合器结构具有每单位长度的大电感和大电容。 支线耦合器结构包括多个四分之一波长传输线，其中至少一个包括高阻抗臂和低阻抗臂。 高阻抗和低阻抗是相对的。 高阻抗臂包括多个窄电池并且具有nL的电感和C / n的电容，并且低阻抗臂包括多个宽电池并且具有L / n的电感和nC的电容。 宽和窄的单元彼此相对，并且宽和窄的单元彼此相邻以形成具有阶梯不连续替代宽度的信号层。

    SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE
    8.
    发明申请
    SOLUTIONS FOR ON-CHIP MODELING OF OPEN TERMINATION OF FRINGE CAPACITANCE 有权
    用于片上电容开机终止的芯片建模解决方案

    公开(公告)号：US20120317530A1

    公开(公告)日：2012-12-13

    申请号：US13158562

    申请日：2011-06-13

    申请人： Michael P. Keene ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

    发明人： Michael P. Keene ,  Guoan Wang ,  Wayne H. Woods, JR. ,  Jiansheng Xu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5081

    摘要： A computer-implemented method of generating a library object for an integrated circuit design is disclosed. In one embodiment, the method includes: analyzing a pair of integrated circuit design objects for fringe capacitance effects between the pair of integrated circuit design objects; and generating the library object accounting for the fringe capacitance effects prior to completion of a layout design for the integrated circuit design.

    摘要翻译： 公开了一种用于生成用于集成电路设计的库对象的计算机实现的方法。 在一个实施例中，该方法包括：分析一对集成电路设计对象，用于一对集成电路设计对象之间的边缘电容效应; 并在完成集成电路设计的布局设计之前生成考虑到边缘电容效应的库对象。

    On chip slow-wave structure, method of manufacture and design structure
    9.
    发明授权
    On chip slow-wave structure, method of manufacture and design structure 有权
    片上慢波结构，制造方法和设计结构

    公开(公告)号：US08130059B2

    公开(公告)日：2012-03-06

    申请号：US12423835

    申请日：2009-04-15

    申请人： Guoan Wang ,  Wayne H. Woods, Jr.

    发明人： Guoan Wang ,  Wayne H. Woods, Jr.

    IPC分类号： H01P1/18

    CPC分类号： H01P9/00

    摘要： An on-chip slow-wave structure that uses multiple parallel signal paths with grounded capacitance structures, method of manufacturing and design structure thereof is provided. The slow wave structure includes a plurality of conductor signal paths arranged in a substantial parallel arrangement. The structure further includes a first grounded capacitance line or lines positioned below the plurality of conductor signal paths and arranged substantially orthogonal to the plurality of conductor signal paths. A second grounded capacitance line or lines is positioned above the plurality of conductor signal paths and arranged substantially orthogonal to the plurality of conductor signal paths. A grounded plane grounds the first and second grounded capacitance line or lines.

    摘要翻译： 提供了采用具有接地电容结构的多个并行信号路径的片上慢波结构，其制造方法和设计结构。 慢波结构包括以大致平行布置布置的多个导体信号路径。 该结构还包括位于多个导体信号路径下方并且基本上正交于多个导体信号路径布置的第一接地电容线或线。 第二接地电容线或线路位于多个导体信号路径上方并且基本上正交于多个导体信号路径布置。 接地平面接地第一和第二接地电容线或线路。

    Circuit structure and design structure for an optionally switchable on-chip slow wave transmission line band-stop filter and a method of manufacture
    10.
    发明授权
    Circuit structure and design structure for an optionally switchable on-chip slow wave transmission line band-stop filter and a method of manufacture 有权
    用于可选择切换的片上慢波传输线带阻滤波器的电路结构和设计结构以及制造方法

    公开(公告)号：US08106728B2

    公开(公告)日：2012-01-31

    申请号：US12424110

    申请日：2009-04-15

    申请人： Hanyi Ding ,  Kwan H. Lam ,  Guoan Wang ,  Wayne H. Woods, Jr.

    发明人： Hanyi Ding ,  Kwan H. Lam ,  Guoan Wang ,  Wayne H. Woods, Jr.

    IPC分类号： H01P3/08 ,  H01P1/203

    CPC分类号： H01P1/203 ,  Y10T29/49155

    摘要： The present invention generally relates to a circuit structure, design structure and method of manufacturing a circuit, and more specifically to a circuit structure and design structure for an on-chip slow wave transmission line band-stop filter and a method of manufacture. A structure includes an on-chip transmission line stub comprising a conditionally floating structure structured to provide increased capacitance to the on-chip transmission line stub when the conditionally floating structure is connected to ground.

    摘要翻译： 本发明一般涉及一种电路结构，电路制造的设计结构和方法，更具体地涉及用于片上慢波传输线带阻滤波器的电路结构和设计结构以及制造方法。 一种结构包括片上传输线短截线，其包括有条件浮动结构，其被构造为当有条件浮动结构连接到地时为片上传输线短截线提供增加的电容。