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26 条记录 (耗时 0.039 秒)

    Applications of cascading DSP slices
    5.
    发明授权
    Applications of cascading DSP slices 有权
    级联DSP片的应用

    公开(公告)号：US07567997B2

    公开(公告)日：2009-07-28

    申请号：US11019518

    申请日：2004-12-21

    申请人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    发明人： James M. Simkins ,  Steven P. Young ,  Jennifer Wong ,  Bernard J. New ,  Alvin Y. Ching

    IPC分类号： G06F7/48

    CPC分类号： G06F7/5443

    摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

    摘要翻译： 在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。 该IC允许实现一些基本的数学函数，例如加，减，乘和除。 可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

    Clock-gating circuit for reducing power consumption
    8.
    发明授权
    Clock-gating circuit for reducing power consumption 有权
    时钟门控电路，用于降低功耗

    公开(公告)号：US06204695B1

    公开(公告)日：2001-03-20

    申请号：US09336357

    申请日：1999-06-18

    申请人： Peter H. Alfke ,  Alvin Y. Ching ,  Scott O. Frake ,  Jennifer Wong ,  Steven P. Young

    发明人： Peter H. Alfke ,  Alvin Y. Ching ,  Scott O. Frake ,  Jennifer Wong ,  Steven P. Young

    IPC分类号： H03H19096

    CPC分类号： G06F1/10

    摘要： A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

    摘要翻译： 为逻辑器件提供时钟选通电路，可降低器件资源需求，消除用户定义自己的时钟选通电路的需要，并消除不期望的时钟信号干扰，如毛刺和欠压脉冲。 在一个实施例中，时钟选通电路包括用于接收输入时钟信号的输入端; 用于接收时钟使能信号的输入端; 存储锁存器，其耦合以接收所述输入时钟信号和所述时钟使能信号，并且作为响应，提供时钟门控制信号; 以及耦合以接收输入时钟信号和时钟门控制信号的逻辑门。 逻辑门选择地响应于时钟门控制信号路由输入时钟信号，由此提供输出时钟信号。

    Digital signal processing block having a wide multiplexer
    9.
    发明授权
    Digital signal processing block having a wide multiplexer 有权
    具有宽多路复用器的数字信号处理块

    公开(公告)号：US07865542B2

    公开(公告)日：2011-01-04

    申请号：US11433120

    申请日：2006-05-12

    申请人： Bernard J. New ,  Vasisht Mantra Vadi ,  Jennifer Wong ,  Alvin Y. Ching ,  John M. Thendean ,  Anna Wing Wah Wong ,  James M. Simkins

    发明人： Bernard J. New ,  Vasisht Mantra Vadi ,  Jennifer Wong ,  Alvin Y. Ching ,  John M. Thendean ,  Anna Wing Wah Wong ,  James M. Simkins

    IPC分类号： G06F7/38

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

    摘要翻译： 一种数字信号处理块，具有：1）第一数字信号处理元件，包括：第一多路复用器的第一多路复用器，所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元，所述第一算术逻辑单元被配置为用于相加; 以及2）第二数字信号处理元件，包括：第二多路复用器的第二多路复用器，所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器，所述第二运算单元被配置为相加。