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    First-in, first-out memory system with reduced cycle latency
    2.
    发明授权
    First-in, first-out memory system with reduced cycle latency 有权
    先进先出的内存系统，缩短了周期延迟

    公开(公告)号：US07254677B1

    公开(公告)日：2007-08-07

    申请号：US10839402

    申请日：2004-05-04

    申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

    发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

    IPC分类号： G06F12/00

    CPC分类号： G06F5/10

    摘要： A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.

    摘要翻译： 嵌入在可编程逻辑器件中的先进先出（“FIFO”）存储器系统具有耦合到输出寄存器的嵌入式FIFO存储器阵列。 如果嵌入式FIFO存储器为空，则写入FIFO存储器系统的第一个字被预取到输出寄存器。 如果在启用READ ENABLE时，如果第一个字可用于从输出寄存器读取，则第一个字检测电路会断言DATA VALID信号。 在替代实施例中，第一个字被预取到输出寄存器的输出，并且可以在READ ENABLE被声明之前被读取。

    First-in, first-out buffer system in an integrated circuit
    3.
    发明授权
    First-in, first-out buffer system in an integrated circuit 有权
    先进先出的缓冲系统在集成电路中

    公开(公告)号：US07161849B1

    公开(公告)日：2007-01-09

    申请号：US11140019

    申请日：2005-05-27

    申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

    发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

    IPC分类号： G11C7/10

    CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/126

    摘要： An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.

    摘要翻译： 具有嵌入式先进先出（“FIFO”）存储器系统的集成电路使用嵌入式块随机存取存储器（“BRAM”）。 计数器在读和写时钟域都工作。 二进制加法器将第一选择的偏移值和第一指针地址相加，并将和转换为第一灰度代码值。 将第一灰度代码值与表示第二指针地址的第二灰度代码值进行比较。 如果第一灰度代码值等于第二灰度代码值，则将比较器的输出提供给在正确的时钟域中产生状态标志（例如ALMOST FULL或ALMOST EMPTY）的逻辑块。

    First-in, first-out buffer system in an integrated circuit
    4.
    发明授权
    First-in, first-out buffer system in an integrated circuit 有权
    先进先出的缓冲系统在集成电路中

    公开(公告)号：US06934198B1

    公开(公告)日：2005-08-23

    申请号：US10838957

    申请日：2004-05-04

    申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

    发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

    IPC分类号： G06F5/14 ,  G11C7/00

    CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/126

    摘要： An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.

    摘要翻译： 具有嵌入式先进先出（“FIFO”）存储器系统的集成电路使用嵌入式块随机存取存储器（“BRAM”）。 计数器在读和写时钟域都工作。 二进制加法器将第一选择的偏移值和第一指针地址相加，并将和转换为第一灰度代码值。 将第一灰度代码值与表示第二指针地址的第二灰度代码值进行比较。 如果第一灰度代码值等于第二灰度代码值，则将比较器的输出提供给在正确的时钟域中产生状态标志（例如ALMOST FULL或ALMOST EMPTY）的逻辑块。

    Almost full, almost empty memory system
    5.
    发明授权
    Almost full, almost empty memory system 有权
    几乎完整，几乎空的内存系统

    公开(公告)号：US06956776B1

    公开(公告)日：2005-10-18

    申请号：US10839201

    申请日：2004-05-04

    申请人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

    发明人： Wayson J. Lowe ,  Eunice Y. D. Hao ,  Tony K. Ngai ,  Peter H. Alfke

    IPC分类号： G06F5/14 ,  G11C7/00

    CPC分类号： G06F5/14 ,  G06F2205/102 ,  G06F2205/106 ,  G06F2205/126

    摘要： A buffer memory status detection circuit has a binary logic gate (e.g. an OR gate) coupled to a comparator output signal that is asserted when a sum of a first address pointer of a FIFO memory array plus a first offset equals a second address pointer, and to a reset signal. Binary logic provides a binary output (i.e. “0” or “1”) in a first clock domain to two synchronization registers in series that convert the output to a second clock domain. An optional pipeline register improves timing of the output in the second clock domain, and is particularly desirable for use with high-speed clocks.

    摘要翻译： 缓冲存储器状态检测电路具有耦合到比较器输出信号的二进制逻辑门（例如或门），当FIFO存储器阵列的第一地址指针和第一偏移的和等于第二地址指针时，比较器输出信号被置位;以及 到复位信号。 二进制逻辑将第一时钟域中的二进制输出（即“0”或“1”）提供给将输出转换为第二时钟域的串联的两个同步寄存器。 可选的流水线寄存器提高了第二个时钟域的输出时序，特别适用于高速时钟。

    Self-repairing redundancy for memory blocks in programmable logic devices
    7.
    发明授权
    Self-repairing redundancy for memory blocks in programmable logic devices 有权
    可编程逻辑器件中的存储器块的自修复冗余

    公开(公告)号：US07216277B1

    公开(公告)日：2007-05-08

    申请号：US10717040

    申请日：2003-11-18

    申请人： Tony K. Ngai ,  Jennifer Wong ,  Wayson J. Lowe

    发明人： Tony K. Ngai ,  Jennifer Wong ,  Wayson J. Lowe

    IPC分类号： G01R31/28 ,  G11C29/00

    CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/846

    摘要： Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.

    摘要翻译： 可编程逻辑器件（PLD），包括自修复RAM电路，以及自动替换RAM阵列中有缺陷的列的方法。 包括冗余列的RAM电路在PLD配置顺序期间使用内置的自检（BIST）过程进行测试。 如果检测到有缺陷的列，则错误标志被存储在相关联的易失性存储器电路中。 BIST程序完成后，PLD配置过程继续。 错误标志的存在导致配置数据绕过故障列，并直接传递到替换列。 配置过程继续，直到电路的其余部分被配置，包括冗余列。 在其他实施例中，独立于PLD配置过程启动BIST过程。 当检测到有缺陷的列时，以对用户透明的方式，将数据从有缺陷的列分流到冗余列的用户操作恢复。

    Dual port random-access-memory circuitry
    8.
    再颁专利
    Dual port random-access-memory circuitry 有权
    双端口随机存取存储器电路

    公开(公告)号：USRE41325E1

    公开(公告)日：2010-05-11

    申请号：US12363461

    申请日：2009-01-30

    申请人： Haiming Yu ,  Tony K. Ngai ,  Kok Heng Choe

    发明人： Haiming Yu ,  Tony K. Ngai ,  Kok Heng Choe

    IPC分类号： G11C11/00

    CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/1075 ,  G11C8/16 ,  G11C8/18

    摘要： Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

    摘要翻译： 提供了包括位线电压钳位电路的双端口存储器阵列电路。 钳位电路包含用于启用和禁用钳位电路的控制晶体管。 钳位电路还包含稳压晶体管和反馈路径。 当在双端口存储器阵列的另一端口执行读取操作时在双端口存储器阵列的一个端口上执行写入操作时，位线电压钳位电路防止读取端口位线上的电压下降 太低。 即使写入的存储单元受到过程，电压和温度的变化的不利影响，也可以快速执行写入操作。

    Method and apparatus for determining clock uncertainties
    9.
    发明授权
    Method and apparatus for determining clock uncertainties 有权
    确定时钟不确定度的方法和装置

    公开(公告)号：US08739099B1

    公开(公告)日：2014-05-27

    申请号：US12176379

    申请日：2008-07-20

    申请人： Victor R. Maruri ,  Boon Jin Ang ,  Henry Y. Lui ,  Surinder Singh ,  Thow Pang Chong ,  Tony K. Ngai

    发明人： Victor R. Maruri ,  Boon Jin Ang ,  Henry Y. Lui ,  Surinder Singh ,  Thow Pang Chong ,  Tony K. Ngai

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5031 ,  G06F2217/62

    摘要： A method for determining clock uncertainties is provided. The method includes identifying clock transfer types between registers from an integrated circuit design and identifying contributors to the clock uncertainties for each of the clock transfers. The jitter associated with each identified contributor is calculated for both set-up time and hold time. This calculated jitter is incorporated into a slack calculation to determine whether timing constraints are met for a circuit design.

    摘要翻译： 提供了一种确定时钟不确定度的方法。 该方法包括从集成电路设计中识别寄存器之间的时钟传输类型，并且识别每个时钟传输的时钟不确定性的贡献者。 针对建立时间和保持时间计算与每个识别的贡献者相关联的抖动。 该计算的抖动被并入到松弛计算中以确定电路设计是否满足时序约束。

    Dual port random-access-memory circuitry
    10.
    发明授权
    Dual port random-access-memory circuitry 有权
    双端口随机存取存储器电路

    公开(公告)号：US07471588B2

    公开(公告)日：2008-12-30

    申请号：US11506254

    申请日：2006-08-18

    申请人： Haiming Yu ,  Tony K. Ngai ,  Kok Heng Choe

    发明人： Haiming Yu ,  Tony K. Ngai ,  Kok Heng Choe

    IPC分类号： G11C11/00

    CPC分类号： G11C7/12 ,  G11C7/04 ,  G11C7/1075 ,  G11C8/16 ,  G11C8/18

    摘要： Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

    摘要翻译： 提供了包括位线电压钳位电路的双端口存储器阵列电路。 钳位电路包含用于启用和禁用钳位电路的控制晶体管。 钳位电路还包含稳压晶体管和反馈路径。 当在双端口存储器阵列的另一端口执行读取操作时在双端口存储器阵列的一个端口上执行写入操作时，位线电压钳位电路防止读取端口位线上的电压下降 太低。 即使写入的存储单元受到过程，电压和温度的变化的不利影响，也可以快速执行写入操作。