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公开(公告)号：US08924513B2
公开(公告)日：2014-12-30
申请号：US12831326
申请日：2010-07-07
申请人： Evangelos S Eleftheriou , Robert Haas , Xiaoyu Hu , Ilias Iliadis
发明人： Evangelos S Eleftheriou , Robert Haas , Xiaoyu Hu , Ilias Iliadis
CPC分类号： H04L67/1095 , H04L61/1582 , H04L67/1097 , H04L69/28
摘要： A pseudo peer-to-peer network system including several clients, each adapted to execute a path driver program. A path driver program is provided, including the steps of locating storage peers connected to the network via a network interface for storing or accessing data items provided in memories of storage peers by means of a global address table. The global address table is updated periodically by at least one configuration server of the pseudo peer-to-peer network. The network further includes at least one time server, which generates a global time clock to which local time clocks of all storage peers of the pseudo peer-to-peer network are synchronized such that a global address table updated by the configuration server is activated by all storage peers at the same scheduled time to be consistent throughout the pseudo peer-to-peer network at all times.
摘要翻译： 一种包括几个客户机的伪对等网络系统，每个客户端适于执行路径驱动程序。 提供一种路径驱动程序，包括通过网络接口定位连接到网络的存储对等体的步骤，用于通过全局地址表存储或访问在存储对等体的存储器中提供的数据项。 全局地址表由伪对等网络的至少一个配置服务器周期性地更新。 该网络还包括至少一个时间服务器，其生成全局时钟，伪对等网络的所有存储对等体的本地时钟同步到该全局时钟，使得由配置服务器更新的全局地址表由 所有存储对等体在相同的调度时间内始终在整个伪对等网络中保持一致。
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公开(公告)号：US08370712B2
公开(公告)日：2013-02-05
申请号：US12835783
申请日：2010-07-14
申请人： Evangelos S Eleftheriou , Ilias Iliadis , Robert Haas , Xiaoyu Hu
发明人： Evangelos S Eleftheriou , Ilias Iliadis , Robert Haas , Xiaoyu Hu
CPC分类号： G06F11/1068 , G11C16/349 , G11C16/3495
摘要： A computer-implemented method of managing a memory of a non-volatile solid state memory device by balancing write/erase cycles among blocks to level block usage. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device, wherein the error is correctable by error-correcting code; and programming the memory unit according to the monitored occurrence of the error; wherein the step of monitoring the occurrence of an error is carried out for at least one block; and wherein said step of programming comprises wear-leveling the monitored block according the error monitored for the monitored block. A computer system and a computer program-product is also provided.The non-volatile solid state memory device includes: a memory unit having data stored therein; and a controller with a logic for programming the memory unit according to a monitored occurrence of an error during a read operation. The method includes: monitoring an occurrence of an error during a read operation in a memory unit of the device; and programming the memory unit according to the monitored occurrence of the error.
摘要翻译： 一种计算机实现的通过平衡块之间的写入/擦除循环来平衡块使用来管理非易失性固态存储器件的存储器的方法。 该方法包括：在设备的存储器单元中的读取操作期间监视错误的发生，其中可通过纠错码校正错误; 并根据所监视的错误发生来对存储器单元进行编程; 其中，针对至少一个块执行监视错误发生的步骤; 并且其中所述编程步骤包括根据所监视的块监测的误差来磨损所监视的块。 还提供了计算机系统和计算机程序产品。 非易失性固态存储装置包括：具有存储在其中的数据的存储单元; 以及控制器，具有用于根据在读取操作期间监视的错误发生来对存储器单元进行编程的逻辑。 该方法包括：在设备的存储器单元中的读取操作期间监视错误的发生; 并根据监视出现的错误对存储器单元进行编程。
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公开(公告)号：US08443273B2
公开(公告)日：2013-05-14
申请号：US12750350
申请日：2010-03-30
IPC分类号： G06F11/00
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10379 , G11B20/10509 , G11B2220/2516
摘要： According to one embodiment, a data detection system includes a coefficient-and-variance engine for selecting which infinite impulse response (IIR) filter and prediction error variance to process and store at any time, and a maximum-likelihood sequence detector. The coefficient-and-variance engine comprises a filter bank storing a plurality of IIR filters that represent a plurality of data-dependent noise whitening or noise prediction filters; a least-mean square (LMS) engine for adapting each IIR filter to actual noise conditions: a variance hank storing a plurality of prediction error variance values; and a data-dependent prediction error variance computation unit which updates the plurality of prediction error variance values. The maximum-likelihood sequence detector includes a metric computation unit that employs the plurality of IIR filters in the filter bank and the plurality of prediction error variances in the variance bank to adaptively compute detector branch metrics. Other systems and methods are also described in other embodiments.
摘要翻译： 根据一个实施例，数据检测系统包括用于选择在任何时间处理和存储的无限脉冲响应（IIR）滤波器和预测误差方差的系数和方差引擎和最大似然序列检测器。 系数和方差引擎包括存储多个表示多个数据相关噪声白化或噪声预测滤波器的IIR滤波器的滤波器组; 用于使每个IIR滤波器适应于实际噪声条件的最小均方（LMS）引擎：存储多个预测误差方差值的方差汉克; 以及数据相关预测误差方差计算单元，其更新所述多个预测误差方差值。 最大似然序列检测器包括在滤波器组中采用多个IIR滤波器的度量计算单元，并且方差库中的多个预测误差方差自适应地计算检测器分支度量。 其他系统和方法也在其他实施例中描述。
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公开(公告)号：US06812867B2
公开(公告)日：2004-11-02
申请号：US10455696
申请日：2003-06-05
申请人： Roy D Cideciyan , Ajay Dholakia , Evangelos S Eleftheriou , Richard L Galbraith , Thomas Mittelholzer , Travis R Oenning , David J Stanek
发明人： Roy D Cideciyan , Ajay Dholakia , Evangelos S Eleftheriou , Richard L Galbraith , Thomas Mittelholzer , Travis R Oenning , David J Stanek
IPC分类号： H03M700
CPC分类号： H03M7/46 , G11B20/1426 , G11B2020/1446 , H03M5/145
摘要： Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream. Counterpart modulation decoders and decoding apparatus are also described.
摘要翻译： 描述了一种具有有限状态机的调制编码器，用于将输入比特转换成输出比特，其中交替输出比特的数量被限制为j + 1，其中j是输出比特中的预定义的最大转移数， 类似的输出位被限制为k + 1，其中k是输出位中的非转换的预定最大数量。 调制编码器可以用于将输入比特流转换成输出比特流的编码装置。 这种装置可以包括用于将输入比特流分成第一组比特和第二组比特的分区逻辑。 多个上述调制编码器可以连接到用于将第一组位转换为编码输出位的分割逻辑。 组合逻辑可以连接到或每个调制编码器和用于组合编码的输出位和第二组位的分区逻辑以产生输出比特流。 还描述了对位调制解码器和解码装置。
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公开(公告)号：US08441847B2
公开(公告)日：2013-05-14
申请号：US12887850
申请日：2010-09-22
申请人： Evangelos S Eleftheriou , Angeliki Pantazi , Nikolaos Papandreou , Charalampos Pozidis , Abu Sabastian
发明人： Evangelos S Eleftheriou , Angeliki Pantazi , Nikolaos Papandreou , Charalampos Pozidis , Abu Sabastian
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C2013/0054 , G11C2013/0092
摘要： A method and a feedback controller for programming at least one multi-level phase-change memory cell with a programming signal. The method and feedback controller include a sequence of write pulses applied to the multi-level phase change memory cell, wherein the feedback controller adjusts in real time at least one parameter of each write pulse as a function of a determined resistance error of the phase-change memory cell with respect to a desired reference resistance level.
摘要翻译： 一种用于使用编程信号来编程至少一个多电平相变存储器单元的方法和反馈控制器。 方法和反馈控制器包括施加到多电平相变存储器单元的写入脉冲序列，其中反馈控制器实时调整每个写入脉冲的至少一个参数作为所确定的相位阻抗误差的函数， 相对于期望的参考电阻电平改变存储器单元。
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公开(公告)号：US08144414B2
公开(公告)日：2012-03-27
申请号：US12720711
申请日：2010-03-10
CPC分类号： G11B20/1202 , G11B20/1833 , G11B20/1866 , G11B2020/1836 , G11B2020/1853 , G11B2220/93
摘要： Methods and apparatus for interleaving data in a multitrack tape drive and for writing data on a multitrack tape in the tape drive. One method includes: partitioning the data into m(2n+k) data blocks, where each data block has a logical array of rows and columns of data bytes; error-correction coding a row and a column of the logical array to produce an encoded block; assigning the coded row to a respective location in a logical interleave array having L rows and 2n+k columns of locations; and writing a sequence of assigned coded rows simultaneously in respective data tracks on the multitrack tape. The coded row is assigned such that the minimum Euclidean distance on the multitrack tape between the coded rows is maximized. The apparatus includes units for performing the methods and the computer program product includes a program code means for causing a computer to perform the methods.
摘要翻译： 用于在多轨磁带驱动器中交织数据并在磁带驱动器中的多轨磁带上写入数据的方法和装置。 一种方法包括：将数据划分为m（2n + k）个数据块，其中每个数据块具有数据字节的行和列的逻辑阵列; 对逻辑阵列的行和列进行纠错编码以产生编码块; 将编码行分配给具有L行和2n + k列位置的逻辑交错阵列中的相应位置; 以及在多轨磁带上的相应数据轨道中同时写入分配的编码行序列。 分配编码行使得编码行之间的多轨磁带上的最小欧几里得距离最大化。 所述装置包括用于执行所述方法的单元，并且所述计算机程序产品包括用于使计算机执行所述方法的程序代码装置。
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公开(公告)号：US06665349B1
公开(公告)日：2003-12-16
申请号：US09478564
申请日：2000-01-06
IPC分类号： H04L2302
CPC分类号： H04L27/2608 , H04L5/143 , H04L27/2626 , H04L27/2647
摘要： Transmission techniques suitable for use in digital subscriber line (DSL) systems such as very high rate digital subscriber line (VDSL) systems are described. One embodiment of the present invention describes a transmission technique related to OFDM from high-speed transmission over twisted-pair cables. The scheme, also known as filtered multitone modulation (FMT), exhibits significantly lower spectral overlapping between adjacent subchannels and provides higher transmission efficiency than discrete multitone modulation (DMT).
摘要翻译： 描述了适用于数字用户线（DSL）系统的传输技术，例如超高速数字用户线（VDSL）系统。 本发明的一个实施例描述了通过双绞线电缆从高速传输中与OFDM相关的传输技术。 该方案也称为滤波多频调制（FMT），在相邻子信道之间显示出较低的频谱重叠，并提供比离散多音调制（DMT）更高的传输效率。
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