公开(公告)号：US10191110B2

公开(公告)日：2019-01-29

申请号：US15006570

申请日：2016-01-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Kumar Abhishek ,  Regis Gubian ,  Sakshi Gupta ,  Sunny Gupta ,  Kushal Kamal

IPC: G01R31/28 ,  G05F3/08

Abstract: An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. The disclosed test method provides for more complete testing of the integrated circuit.

公开(公告)号：US09599672B2

公开(公告)日：2017-03-21

申请号：US14566833

申请日：2014-12-11

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Kumar Abhishek ,  Anurag Jindal ,  Nishant Madan ,  Mayank Tutwani

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318552 ,  G01R31/318541

Abstract: An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.

公开(公告)号：US10242955B2

公开(公告)日：2019-03-26

申请号：US15250644

申请日：2016-08-29

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Mohit Arora ,  Kumar Abhishek ,  Prashant Bhargava ,  Rakesh Pandey

IPC: H01L23/00 ,  G01R31/02 ,  G06F21/87 ,  H03K3/0233 ,  H03K3/84 ,  H03K19/003 ,  H05K1/02

Abstract: An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.

公开(公告)号：US09559671B1

公开(公告)日：2017-01-31

申请号：US14972350

申请日：2015-12-17

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Srikanth Jagannathan ,  Nihaar N. Mahatme ,  Kumar Abhishek

IPC: H03K3/289 ,  H03K3/037 ,  H03K17/687

CPC classification number: H03K17/6872 ,  H03K3/0375 ,  H03K3/35625

Abstract: A master slave storage circuit can include a first master portion coupled to a first master data storage node and a first slave portion coupled to a first slave data storage node. The first master portion can comprise one of a first master latch or a first master capacitive element coupled to the first master data storage node and the first slave portion comprises one of a first slave latch or a first slave capacitive element coupled to the first slave data storage node. If the first master portion comprises the first master latch, the first slave portion comprises the first slave capacitive element, and if the first master portion comprises the first master capacitive element, the first slave portion comprises the first slave latch.

Abstract translation: 主从存储电路可以包括耦合到第一主数据存储节点的第一主部分和耦合到第一从数据存储节点的第一从部分。 第一主部分可以包括耦合到第一主数据存储节点的第一主锁存器或第一主电容元件中的一个，并且第一从部件包括耦合到第一从数据的第一从锁存器或第一从电容元件中的一个 存储节点。 如果第一主部分包括第一主锁存器，则第一从部件包括第一从电容元件，如果第一主部件包括第一主电容元件，则第一从部件包括第一从锁存器。

公开(公告)号：US20140122010A1

公开(公告)日：2014-05-01

申请号：US13665902

申请日：2012-10-31

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Kushal Kamal ,  Kumar Abhishek ,  Sunny Gupta

IPC: G01R31/26 ,  G06F19/00

CPC classification number: G09G3/006 ,  G09G3/18

Abstract: A system and method for verifying the electrical behavior of a liquid crystal display (LCD) driver circuit connected to LCD segments of an electronic circuit includes generating test patterns for verifying the LCD driver circuit. The LCD driver circuit generates LCD stimuli in the form of electrical current based on the test patterns. The current is applied to front and back planes of each LCD segment. Root mean square (RMS) voltages of each LCD segment are determined and compared with predetermined threshold values to verify the state of each LCD segment.

Abstract translation: 用于验证连接到电子电路的LCD段的液晶显示（LCD）驱动器电路的电气行为的系统和方法包括产生用于验证LCD驱动器电路的测试图案。 LCD驱动电路基于测试图形产生电流形式的LCD刺激。 电流适用于每个LCD段的前后平面。 确定每个LCD段的均方根（RMS）电压并与预定阈值进行比较以验证每个LCD段的状态。

公开(公告)号：US09697065B1

公开(公告)日：2017-07-04

申请号：US15064641

申请日：2016-03-09

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Kumar Abhishek ,  Steven K. Watkins ,  Garima Sharda ,  James M. Giandelone ,  Stefano Pietri ,  Thomas H. Luedeke

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0745 ,  G06F11/22 ,  G06F13/00

Abstract: A method for managing a reset process in a processing system is provided. The method includes enabling a watch dog unit based on a power-on reset (POR) event. A stuck in reset condition indication is received at the watch dog unit and used to determine whether the received reset condition indication corresponds to an unintentional reset condition. If the received reset condition indication is an indication of an unintentional reset condition, a watch dog POR trigger signal is generated and a reset state machine is repeated for system recovery.

公开(公告)号：US09473121B1

公开(公告)日：2016-10-18

申请号：US14799903

申请日：2015-07-15

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Kumar Abhishek ,  Gaurav Goyal ,  Syed Shakir Iqbal

IPC: H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/35625 ,  G01R31/318541 ,  H03K3/356156

Abstract: A scannable flip-flop circuit and method for low power scan operation are provided. The scannable flip-flop includes a flip-flop for receiving an input signal, and for generating a flip-flop output signal. The scannable flip-flop also includes a voltage selection circuit coupled to the flip-flop. The voltage selection circuit supplies a first voltage to the flip-flop during a first state of a voltage selection signal, and supplies a second voltage to the flip-flop during a second state of the voltage selection signal. A series of scannable flip-flops may be arranged in a scan chain for testing during a scan test mode.

Abstract translation: 提供了可扫描触发器电路和用于低功率扫描操作的方法。 可扫描触发器包括用于接收输入信号并用于产生触发器输出信号的触发器。 可扫描触发器还包括耦合到触发器的电压选择电路。 电压选择电路在电压选择信号的第一状态期间向触发器提供第一电压，并且在电压选择信号的第二状态期间向触发器提供第二电压。 可以在扫描链中布置一系列可扫描触发器，以在扫描测试模式期间进行测试。