公开(公告)号：US06525973B1

公开(公告)日：2003-02-25

申请号：US10020536

申请日：2001-12-12

申请人： Farshid Shokouhi ,  Michael G. Ahrens

发明人： Farshid Shokouhi ,  Michael G. Ahrens

IPC分类号： G11C700

CPC分类号： G11C29/12 ,  G11C29/10

摘要： A one-shot system for loading a bitline shift register with a typical test pattern is described. Each bitline latch within the bitline shift register is augmented with a one-shot circuit that may pull-up or pull-down the value stored in the bitline latch. The choice of a particular memory test pattern dictates the control of the one-shot circuit.

摘要翻译： 描述用于加载具有典型测试图案的位线移位寄存器的单触发系统。 位线移位寄存器内的每个位线锁存器都可以通过上拉或下拉存储在位线锁存器中的值的单触发电路来增加。 特定存储器测试模式的选择指示单触发电路的控制。

公开(公告)号：US06249458B1

公开(公告)日：2001-06-19

申请号：US09603462

申请日：2000-06-22

申请人： Farshid Shokouhi ,  Michael G. Ahrens ,  Ben Y. Sheen

发明人： Farshid Shokouhi ,  Michael G. Ahrens ,  Ben Y. Sheen

IPC分类号： G11C1600

CPC分类号： G11C16/12 ,  G11C16/30

摘要： A floating gate memory device that includes a switching circuit for selectively transferring two or more negative voltages to a common node (e.g., to the negative pole of a driver circuit). The switching circuit includes two switches respectively connected between the two negative voltages and the common node. Each of the switches includes series-connected triple-well NMOS transistors that provide a dual-isolation structure between the common node the negative voltage sources. An optional triple P-well resistor is provided between the series-connected triple-well NMOS transistors in each of the switches that includes a deep N-well region biased by a system voltage source (e.g., VCC) to reverse bias the central P-well region.

摘要翻译： 一种浮动栅极存储器件，其包括用于选择性地将两个或更多个负电压传送到公共节点（例如，驱动电路的负极）的开关电路。 开关电路包括分别连接在两个负电压和公共节点之间的两个开关。 每个开关包括串联连接的三阱NMOS晶体管，其在公共节点之间提供负电压源之间的双重隔离结构。 在每个开关中的串联连接的三阱NMOS晶体管之间提供可选的三重P阱电阻器，其包括由系统电压源（例如VCC）偏置的深N阱区域，以反向偏置中心P- 井区。

公开(公告)号：US06233177B1

公开(公告)日：2001-05-15

申请号：US09603458

申请日：2000-06-22

申请人： Farshid Shokouhi ,  Michael G. Ahrens

发明人： Farshid Shokouhi ,  Michael G. Ahrens

IPC分类号： G11C1600

CPC分类号： G11C16/12 ,  G11C16/24

摘要： A floating gate memory device that includes a column latch circuit that is isolated from a series of bitlines by PMOS pass transistors controlled by a bitline latch switch circuit. The bitline latch switch circuit selectively applies either +5 V or −2 V signals to the gate terminals of the PMOS pass transistors, thereby allowing the PMOS pass transistors to selectively pass 0 (zero) Volts during, for example, program operations. A −2 V charge pump is activated to generate the −2 V signal during operations requiring 0 Volt bitline voltages, and is turned off during all other operations.

摘要翻译： 一种浮动栅极存储器件，其包括通过由位线锁存开关电路控制的PMOS传输晶体管与一系列位线隔离的列锁存电路。 位线锁存开关电路选择性地向PMOS传输晶体管的栅极端施加+ 5V或-2V信号，从而允许PMOS传输晶体管在例如程序操作期间选择性地通过0（零）伏特。 在需要0伏位线电压的操作期间，激活-2 V电荷泵产生-2 V信号，并在所有其他操作期间关闭。

公开(公告)号：US07047467B1

公开(公告)日：2006-05-16

申请号：US10121064

申请日：2002-04-11

申请人： Arthur H. Khu ,  Farshid Shokouhi ,  Conrad A. Theron

发明人： Arthur H. Khu ,  Farshid Shokouhi ,  Conrad A. Theron

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318555

摘要： According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.

摘要翻译： 根据本发明，具有控制器的JTAG兼容芯片具有接收在TDI输入引脚上提供的数据并形成并行地址和数据指令并将数据通过IO引脚传送到非JTAG芯片的控制器，能够验证数据是否为 通过读取数据并与原始数据进行比较，由非JTAG芯片正确接收。 状态位或位在TDO引脚上移出，用于确定下一个数据将被移位。

公开(公告)号：US06593779B2

公开(公告)日：2003-07-15

申请号：US10238214

申请日：2002-09-09

申请人： Farshid Shokouhi ,  Ben Y. Sheen ,  Qi Lin

发明人： Farshid Shokouhi ,  Ben Y. Sheen ,  Qi Lin

IPC分类号： H03K522

CPC分类号： G11C16/30 ,  G01R19/0084 ,  G11C5/145

摘要： The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of a positive charge pump is begun after the charging of a negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from the negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected. Thus, the comparator generates a trigger signal when the voltage at the node decreases to the second reference voltage. This output signal triggers the pumping of the positive charge pump. By changing the resistance within the resistor chain, the positive charge pumping may be initiated at varying negative voltages. In the present invention, additional resistance is added to or removed from the resistor chain via metal options or switches.

公开(公告)号：US06300839B1

公开(公告)日：2001-10-09

申请号：US09644286

申请日：2000-08-22

申请人： Hassan K. Bazargan ,  Farshid Shokouhi

发明人： Hassan K. Bazargan ,  Farshid Shokouhi

IPC分类号： G05F140

CPC分类号： H02M3/073

摘要： In a charge pump system, the frequency of an oscillator is based on the output signals from a plurality of differential amplifiers. Each differential amplifier receives a different reference voltage as well as a common input voltage derived from the pumped voltage. A predetermined logic signal output by the differential amplifiers modifies, i.e. reduces, an original frequency of the oscillator. In this manner, the charge pump system quickly compensates for any overshoot in the pumped voltage in a manner directly correlated to the magnitude of the pumped voltage. If no differential amplifiers output the predetermined logic signal, then the oscillator generates the original frequency. In this manner, the charge pump system also compensates for any undershoot in the pumped voltage by providing the fastest frequency.

摘要翻译： 在电荷泵系统中，振荡器的频率基于来自多个差分放大器的输出信号。 每个差分放大器接收不同的参考电压以及从泵浦电压得到的公共输入电压。 由差分放大器输出的预定逻辑信号修改振荡器的原始频率，即降低振荡器的原始频率。 以这种方式，电荷泵系统以与泵送电压的大小直接相关的方式快速补偿泵浦电压中的任何过冲。 如果没有差分放大器输出预定的逻辑信号，则振荡器产生原始频率。 以这种方式，电荷泵系统还通过提供最快的频率来补偿泵浦电压中的任何下冲。

公开(公告)号：US06925583B1

公开(公告)日：2005-08-02

申请号：US10043637

申请日：2002-01-09

申请人： Arthur H. Khu ,  Conrad A. Theron ,  Farshid Shokouhi ,  Pushpasheel Tawade

发明人： Arthur H. Khu ,  Conrad A. Theron ,  Farshid Shokouhi ,  Pushpasheel Tawade

IPC分类号： G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318544 ,  G01R31/318555

摘要： According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data to go through the boundary scan register chain of the JTAG-compliant chip. This controller is used to program, erase, and read the other chip. For a non-JTAG flash memory device, the controller in the JTAG-compliant chip generates the necessary programming signal sequences, and applies them to the non-JTAG chip without going through the JTAG boundary scan circuitry.

摘要翻译： 根据本发明，JTAG兼容芯片还具有控制器，该控制器接收在TDI输入引脚上提供的数据，形成并行地址和数据指令，并将数据通过IO引脚传送到非JTAG芯片，而不需要数据 通过JTAG兼容芯片的边界扫描寄存器链。 该控制器用于对其他芯片进行编程，擦除和读取。 对于非JTAG闪存器件，JTAG兼容芯片中的控制器产生必要的编程信号序列，并将其应用于非JTAG芯片，而无需通过JTAG边界扫描电路。

公开(公告)号：US06369612B1

公开(公告)日：2002-04-09

申请号：US09626697

申请日：2000-07-27

申请人： Farshid Shokouhi

发明人： Farshid Shokouhi

IPC分类号： H03K19094

CPC分类号： H03K19/018521

摘要： A high voltage level-shifter that facilitates the conversion of typical positive logic input signal voltages to non-positive (i.e., at or below ground) output signal voltages. The high voltage level-shifter is separated into two voltage shifting circuits that are connected in parallel between a circuit input terminal and a circuit output terminal. The first voltage shifting circuit includes an isolation switch (e.g., a pass transistor) connected between a positive voltage source and a positive supply rail of an output driver. The negative supply rail of the output driver is connected to one of the non-positive voltage sources. An output control circuit controls the isolation switch to couple the positive voltage source to the positive supply rail of the output driver only when the negative voltage source is driven onto the circuit output terminal (i.e., in response to a logic “1” input signal).

摘要翻译： 有助于将典型的正逻辑输入信号电压转换成非正（即，接地或低于地）的输出信号电压的高电压电平转换器。 高压电平移位器被分成两个并联在电路输入端和电路输出端之间的电压移位电路。 第一电压移位电路包括连接在正电压源和输出驱动器的正电源轨之间的隔离开关（例如，通过晶体管）。 输出驱动器的负电源线连接到非正电压源之一。 只有当负电压源被驱动到电路输出端（即响应于逻辑“1”输入信号）时，输出控制电路才控制隔离开关将正电压源耦合到输出驱动器的正电源轨， 。

公开(公告)号：US07047352B1

公开(公告)日：2006-05-16

申请号：US10230920

申请日：2002-08-28

申请人： Arthur H. Khu ,  Farshid Shokouhi

发明人： Arthur H. Khu ,  Farshid Shokouhi

IPC分类号： G06F12/00

CPC分类号： G06F17/5054 ,  G06F11/1441 ,  G06F12/1425 ,  H03K19/17764 ,  H03K19/17772

摘要： Structure and method for updating a system that includes a memory and a programmable logic device (PLD) retains a default PLD configuration in the memory while a new configuration is being stored in the memory, and thus protect the system from failure in case an interruption occurs while the new configuration is being stored. If a power failure interrupts the storing process, the default PLD configuration is still in the memory and can be re-loaded into the PLD and used when the system is re-started to make a further attempt at storing the new configuration. Methods are also disclosed for storing in the memory a configuration for a new PLD before the original PLD is replaced so that system hardware can be updated with minimum effort and disruption, and for dividing a directory structure into protected and unprotected regions.

摘要翻译： 用于更新包括存储器和可编程逻辑器件（PLD）的系统的结构和方法在存储器中存储新的配置的同时在存储器中保留默认PLD配置，并且因此在发生中断的情况下保护系统免于故障 而新的配置正在被存储。 如果电源故障中断存储过程，则默认的PLD配置仍然在存储器中，并且可以重新加载到PLD中，并且当系统重新启动以进一步尝试存储新配置时使用。 还公开了用于在原始PLD被替换之前在存储器中存储用于新PLD的配置的方法，使得可以以最小的努力和中断来更新系统硬件，以及将目录结构划分为受保护和不受保护的区域。

公开(公告)号：US06651199B1

公开(公告)日：2003-11-18

申请号：US09603464

申请日：2000-06-22

申请人： Farshid Shokouhi

发明人： Farshid Shokouhi

IPC分类号： G01R3128

CPC分类号： G01R31/318533 ,  G01R31/318516

摘要： A trigger circuit for an In-System Programmable (ISP) memory device that operates with a JTAG interface. The trigger circuit receives instruction signals from the JTAG control circuitry, and limits the duration of these instruction signals to avoid erroneously repeating ISP programming operations. The trigger circuit includes a first logic circuit, a delay circuit, and a second logic circuit. The first logic circuit generates a logic high output when both the JTAG RUN-TEST and a program instruction signal are simultaneously asserted, and causes the second logic circuit to toggle the limited duration instruction signal into a logic high state. The delay circuit also detects the simultaneous assertion of the JTAG RUN-TEST and a program instruction signal, and generates a cancellation signal after a predetermined number of clock cycles. The cancellation signal causes the second logic circuit to toggle the limited duration instruction signal into a logic low state.

摘要翻译： 用于使用JTAG接口工作的在系统可编程（ISP）存储器件的触发电路。 触发电路接收来自JTAG控制电路的指令信号，并限制这些指令信号的持续时间，以避免错误地重复ISP编程操作。 触发电路包括第一逻辑电路，延迟电路和第二逻辑电路。 当JTAG RUN-TEST和程序指令信号同时置位时，第一逻辑电路产生逻辑高输出，并使第二逻辑电路将有限持续时间指令信号切换到逻辑高状态。 延迟电路还检测JTAG运行测试和程序指令信号的同时置位，并在预定数量的时钟周期之后产生消除信号。 消除信号使得第二逻辑电路将有限持续时间指令信号切换到逻辑低状态。