公开(公告)号：US07895420B2

公开(公告)日：2011-02-22

申请号：US11067357

申请日：2005-02-25

申请人： Farzan Fallah ,  Anup Hosangadi ,  Ryan C. Kastner

发明人： Farzan Fallah ,  Anup Hosangadi ,  Ryan C. Kastner

IPC分类号： G06F9/30 ,  G06F17/14 ,  G06F15/00

CPC分类号： G06F17/12

摘要： A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and then performing kernel extraction and optimization on one or more of the polynomials. One or more common subexpressions associated with the polynomials are identified in order to reduce one or more of the operations.

摘要翻译： 提供了一种用于减少处理环境中的操作的方法，其包括生成一个或多个二进制表示，一个或多个二进制表示被包括在包括一个或多个操作的一个或多个线性方程中。 该方法还包括将一个或多个线性方程转换成一个或多个多项式，然后对一个或多个多项式进行核提取和优化。 识别与多项式相关联的一个或多个公共子表达式以减少一个或多个操作。

公开(公告)号：US20060294169A1

公开(公告)日：2006-12-28

申请号：US11067357

申请日：2005-02-25

申请人： Farzan Fallah ,  Anup Hosangadi ,  Ryan Kastner

发明人： Farzan Fallah ,  Anup Hosangadi ,  Ryan Kastner

IPC分类号： G06F15/00

CPC分类号： G06F17/12

摘要： A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and then performing kernel extraction and optimization on one or more of the polynomials. One or more common subexpressions associated with the polynomials are identified in order to reduce one or more of the operations.

摘要翻译： 提供了一种用于减少处理环境中的操作的方法，其包括生成一个或多个二进制表示，一个或多个二进制表示被包括在包括一个或多个操作的一个或多个线性方程中。 该方法还包括将一个或多个线性方程转换成一个或多个多项式，然后对一个或多个多项式进行核提取和优化。 识别与多项式相关联的一个或多个公共子表达式以减少一个或多个操作。

公开(公告)号：US20070180010A1

公开(公告)日：2007-08-02

申请号：US11331895

申请日：2006-01-13

申请人： Farzan Fallah ,  Anup Hosangadi ,  Ryan Kastner

发明人： Farzan Fallah ,  Anup Hosangadi ,  Ryan Kastner

IPC分类号： G06F17/14

CPC分类号： G06F17/10

摘要： A method for reducing operations in a processing environment is provided that includes generating one or more binary representations. One or more of the binary representations are included in one or more linear equations that include one or more operations. The method also includes converting one or more of the linear equations to one or more polynomials and identifying one or more common subexpressions associated with the polynomials in order to reduce one or more of the operations. The identifying step is facilitated by an algorithm that iteratively selects divisors and then uses the divisors to eliminate common subexpressions among the linear equations. The method can also take into account the delay of expressions while performing the optimization. Further, it can optimize a polynomial to reduce the number of operations. Additionally, it can optimize the exponents of variables.

摘要翻译： 提供了一种用于减少处理环境中的操作的方法，其包括生成一个或多个二进制表示。 一个或多个二进制表示被包括在包括一个或多个操作的一个或多个线性方程中。 该方法还包括将一个或多个线性方程转换为一个或多个多项式并且识别与多项式相关联的一个或多个公共子表达式，以便减少一个或多个操作。 通过迭代地选择除数然后使用除数消除线性方程中的公共子表达式的算法来促进识别步骤。 该方法还可以在执行优化时考虑表达式的延迟。 此外，它可以优化多项式以减少操作次数。 此外，它可以优化变量的指数。

公开(公告)号：US07647514B2

公开(公告)日：2010-01-12

申请号：US11198559

申请日：2005-08-05

申请人： Toru Ishihara ,  Farzan Fallah

发明人： Toru Ishihara ,  Farzan Fallah

IPC分类号： G06F1/32

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/271 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： In one embodiment, a method for reducing power consumption at a cache includes determining a nonuniform architecture for a cache providing an optimum number of cache ways for each cache set in the cache. The nonuniform architecture allows cache sets in the cache to have associativity values that differ from each other. The method also includes implementing the nonuniform architecture in the cache to reduce power consumption at the cache. In another embodiment, the method also includes determining a code placement according to which code is writeable to a memory separate from the cache. The code placement reduces occurrences of inter cache-line sequential flows when the code is loaded from the memory to the cache. The method also includes compiling the code according to the code placement and writing the code to the memory for subsequent loading from the memory to the cache according to the code placement to further reduce power consumption at the cache.

摘要翻译： 在一个实施例中，一种用于降低高速缓存中的功耗的方法包括：为高速缓存中的每个高速缓存集提供最佳数量的高速缓存路径的高速缓存的确定非均匀架构。 非均匀结构允许缓存中的高速缓存集具有彼此不同的关联性值。 该方法还包括在高速缓存中实现非均匀结构以降低高速缓存的功耗。 在另一个实施例中，该方法还包括根据哪个代码可写入与高速缓存分离的存储器来确定代码布局。 当代码从内存加载到高速缓存时，代码布局可以减少缓存间间隔线顺序流的发生。 该方法还包括根据代码放置编译代码，并将代码写入存储器，以便随后根据代码放置从存储器加载到高速缓存，以进一步降低高速缓存的功耗。

公开(公告)号：US07549069B2

公开(公告)日：2009-06-16

申请号：US11377073

申请日：2006-03-15

申请人： Toru Ishihara ,  Farzan Fallah

发明人： Toru Ishihara ,  Farzan Fallah

IPC分类号： G06F1/32 ,  G06F9/455

CPC分类号： G06F17/5022 ,  G06F2217/78

摘要： Techniques are provided for characterizing processor designs and estimating power consumption of software programs executing on processors. A power model of a processor may be obtained by performing simulation using one or more training programs to obtain average power consumption during one or more windows of operation, then using the results to select parameters and coefficients for a processor characterization equation that can estimate power consumption while minimizing error.

摘要翻译： 提供了用于表征处理器设计并估计在处理器上执行的软件程序的功耗的技术。 可以通过使用一个或多个训练程序执行模拟来获得处理器的功率模型，以在一个或多个操作窗口期间获得平均功耗，然后使用结果为可以估计功耗的处理器表征方程选择参数和系数 同时最小化错误。

公开(公告)号：US20070294587A1

公开(公告)日：2007-12-20

申请号：US11421365

申请日：2006-05-31

申请人： Toru Ishihara ,  Farzan Fallah

发明人： Toru Ishihara ,  Farzan Fallah

IPC分类号： G06F11/00

CPC分类号： G06F12/126 ,  G06F12/0864

摘要： In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The generation of the second object code takes into account one or more locations of one or more defects in a cache on a processor such that one or more instructions in the second object code are written only to nondefective locations in the cache.

摘要翻译： 在一个实施例中，一种用于提高具有缺陷高速缓存的处理器的性能的方法包括访问第一目标代码并从第一目标代码产生第二目标代码。 第二目标代码的生成考虑到处理器上的高速缓存中的一个或多个缺陷的一个或多个位置，使得第二目标代码中的一个或多个指令仅写入高速缓存中的无缺陷位置。

公开(公告)号：US07210128B2

公开(公告)日：2007-04-24

申请号：US10270835

申请日：2002-10-14

申请人： Farzan Fallah ,  Indradeep Ghosh

发明人： Farzan Fallah ,  Indradeep Ghosh

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F17/00 ,  G06F7/00

CPC分类号： G06F11/3676 ,  Y10S707/99943 ,  Y10S707/99945

摘要： A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with each record having at least one data dependency, a parent node, and a child node. Each node is linked to a variable. The method computes the value of each variable using the data structure. The method performs tag propagation based, at least in part, on the data dependencies and computed values.

摘要翻译： 用于事件驱动可观察性的方法增强了程序的覆盖率分析，将程序解析为变量和数据依赖性，其中数据依赖性包括分配和操作。 该方法构建具有多个记录的数据结构，每个记录具有至少一个数据依赖性，父节点和子节点。 每个节点链接到一个变量。 该方法使用数据结构计算每个变量的值。 该方法至少部分地基于数据依赖性和计算值执行标签传播。

公开(公告)号：US20070083783A1

公开(公告)日：2007-04-12

申请号：US11198693

申请日：2005-08-05

申请人： Toru Ishihara ,  Farzan Fallah

发明人： Toru Ishihara ,  Farzan Fallah

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F2212/271 ,  Y02D10/13 ,  Y02D10/14

摘要： In one embodiment, a method for reducing power consumption at a cache includes determining a code placement according to which code is writable to a memory separate from a cache. The code placement reduces occurrences of inter cache-line sequential flows when the code is loaded from the memory to the cache. The method also includes compiling the code according to the code placement and writing the code to the memory for subsequent loading from the memory to the cache according to the code placement to reduce power consumption at the cache. In another embodiment, the method also includes determining a nonuniform architecture for the cache providing an optimum number of cache ways for each cache set in the cache. The nonuniform architecture allows cache sets in the cache to have associativity values that differ from each other. The method also includes implementing the nonuniform architecture in the cache to further reduce power consumption at the cache.

摘要翻译： 在一个实施例中，一种用于降低高速缓存功耗的方法包括根据哪个代码可写入与高速缓存分开的存储器来确定代码放置。 当代码从内存加载到高速缓存时，代码布局可以减少缓存间间隔线顺序流的发生。 该方法还包括根据代码放置编译代码并将代码写入存储器，以便随后根据代码放置从存储器加载到高速缓存，以减少高速缓存的功耗。 在另一个实施例中，该方法还包括确定高速缓存的不均匀架构，为高速缓存中的每个高速缓存集提供最佳数量的高速缓存路。 非均匀结构允许缓存中的高速缓存集具有彼此不同的关联性值。 该方法还包括在高速缓存中实现非均匀结构，以进一步降低高速缓存的功耗。

公开(公告)号：US11112965B2

公开(公告)日：2021-09-07

申请号：US16294930

申请日：2019-03-07

申请人： Farzan Fallah

发明人： Farzan Fallah

IPC分类号： G06F3/0488 ,  G06F3/0482 ,  G06F3/023 ,  G06F40/232 ,  G06F40/284

摘要： An input signal corresponding to an action other than a drag on any virtual keyboard causes an erroneous string having at least two characters with an incorrect character other than the last character to be displayed. A second input signal corresponding to a drag on a virtual keyboard triggers entry into an error correction mode. A first incorrect character is located, a corrected input is determined according to an angle and a slide direction of the first drag, and the layout and geometry of the virtual keyboard; the first incorrect character is replaced with the corrected input to provide and display a first corrected string. The replacement of the first incorrect character and the display of the first corrected string occur without input from any source external to the device other than the first and the second input signals.

公开(公告)号：US20090146734A1

公开(公告)日：2009-06-11

申请号：US12263341

申请日：2008-10-31

申请人： Farzan Fallah ,  Ehsan Pakbaznia ,  Massoud Pedram

发明人： Farzan Fallah ,  Ehsan Pakbaznia ,  Massoud Pedram

IPC分类号： G05F1/10 ,  H03K19/00

CPC分类号： H03K19/0019

摘要： In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to ground via a second sleep transistor, a second virtual ground node between the second circuit block and the second sleep transistor, and a transmission gate (TG) or a pass transistor connecting the first virtual ground node to the second virtual ground node to enable charge recycling between the first circuit block and the second circuit block during transitions by the first circuit block from active mode to sleep mode and the second circuit block from sleep mode to active mode or vice versa.

摘要翻译： 在一个实施例中，电路包括经由第一休眠晶体管连接到地的第一电路块，在第一电路块和第一休眠晶体管之间的第一虚拟接地节点，经由第二睡眠晶体管连接到地的第二电路块， 在第二电路块和第二休眠晶体管之间的第二虚拟接地节点以及将第一虚拟接地节点连接到第二虚拟接地节点的传输门（TG）或传输晶体管，以使第一电路块和第二虚拟接地节点之间的电荷再循环 在第一电路块从活动模式转换到休眠模式的过渡期间的电路块，并且第二电路块从睡眠模式转换到活动模式，反之亦然。