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40 条记录 (耗时 0.018 秒)

    PG-gated data retention technique for reducing leakage in memory cells
    1.
    发明授权
    PG-gated data retention technique for reducing leakage in memory cells 失效
    用于减少存储单元泄漏的PG门控数据保留技术

    公开(公告)号：US07447101B2

    公开(公告)日：2008-11-04

    申请号：US11615422

    申请日：2006-12-22

    申请人： Farzan Fallah ,  Behnam Amelifard ,  Massoud Pedram

    发明人： Farzan Fallah ,  Behnam Amelifard ,  Massoud Pedram

    IPC分类号： G11C5/14 ,  G11C11/00

    CPC分类号： G11C11/417

    摘要： A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.

    摘要翻译： 形成存储单元的方法包括将存储单元的电源轨和可操作以接受电源电压的节点之间的第一晶体管耦合。 该方法还包括将第二晶体管耦合在电池的接地导轨和可操作以接受接地的节点之间。 在一个实施例中，该方法包括形成电池以接受选择性地施加的外部电压，其中选择外部电压以最小化电池中的泄漏电流。 在另一个实施例中，该方法包括形成第一和第二晶体管中的至少一个以具有选择的沟道宽度和/或阈值电压以最小化单元中的总泄漏电流。

    PG-Gated Data Retention Technique for Reducing Leakage in Memory Cells
    4.
    发明申请
    PG-Gated Data Retention Technique for Reducing Leakage in Memory Cells 失效
    用于减少记忆细胞渗漏的PG门控数据保留技术

    公开(公告)号：US20080151673A1

    公开(公告)日：2008-06-26

    申请号：US11615422

    申请日：2006-12-22

    申请人： Farzan Fallah ,  Behnam Amelifard ,  Massoud Pedram

    发明人： Farzan Fallah ,  Behnam Amelifard ,  Massoud Pedram

    IPC分类号： G11C5/14

    CPC分类号： G11C11/417

    摘要： A method of forming a memory cell includes coupling a first transistor between a supply rail of a memory cell and a node operable to accept a supply voltage. The method further includes coupling a second transistor between a ground rail of the cell and a node operable to accept a ground. In one embodiment, the method includes forming the cell to accept selectively applied external voltages, wherein the external voltages are selected to minimize leakage current in the cell. In another embodiment, the method includes forming at least one of the first and the second transistors to have a channel width and/or a threshold voltage selected to minimize a total leakage current in the cell.

    摘要翻译： 形成存储单元的方法包括将存储单元的电源轨和可操作以接受电源电压的节点之间的第一晶体管耦合。 该方法还包括将第二晶体管耦合在电池的接地导轨和可操作以接受接地的节点之间。 在一个实施例中，该方法包括形成电池以接受选择性地施加的外部电压，其中选择外部电压以最小化电池中的泄漏电流。 在另一个实施例中，该方法包括形成第一和第二晶体管中的至少一个以具有选择的沟道宽度和/或阈值电压以最小化单元中的总泄漏电流。

    Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) Circuits
    5.
    发明申请
    Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) Circuits 审中-公开
    电源门控互补金属氧化物半导体（CMOS）电路和超级截止CMOS（SCCMOS）电路中的充电回收（CR）

    公开(公告)号：US20090146734A1

    公开(公告)日：2009-06-11

    申请号：US12263341

    申请日：2008-10-31

    申请人： Farzan Fallah ,  Ehsan Pakbaznia ,  Massoud Pedram

    发明人： Farzan Fallah ,  Ehsan Pakbaznia ,  Massoud Pedram

    IPC分类号： G05F1/10 ,  H03K19/00

    CPC分类号： H03K19/0019

    摘要： In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to ground via a second sleep transistor, a second virtual ground node between the second circuit block and the second sleep transistor, and a transmission gate (TG) or a pass transistor connecting the first virtual ground node to the second virtual ground node to enable charge recycling between the first circuit block and the second circuit block during transitions by the first circuit block from active mode to sleep mode and the second circuit block from sleep mode to active mode or vice versa.

    摘要翻译： 在一个实施例中，电路包括经由第一休眠晶体管连接到地的第一电路块，在第一电路块和第一休眠晶体管之间的第一虚拟接地节点，经由第二睡眠晶体管连接到地的第二电路块， 在第二电路块和第二休眠晶体管之间的第二虚拟接地节点以及将第一虚拟接地节点连接到第二虚拟接地节点的传输门（TG）或传输晶体管，以使第一电路块和第二虚拟接地节点之间的电荷再循环 在第一电路块从活动模式转换到休眠模式的过渡期间的电路块，并且第二电路块从睡眠模式转换到活动模式，反之亦然。

    System and method for identifying optimal encoding for a given trace
    6.
    发明申请
    System and method for identifying optimal encoding for a given trace 失效
    用于识别给定迹线的最佳编码的系统和方法

    公开(公告)号：US20060061492A1

    公开(公告)日：2006-03-23

    申请号：US10945330

    申请日：2004-09-20

    申请人： Farzan Fallah ,  Yazdan Aghaghiri ,  Massoud Pedram

    发明人： Farzan Fallah ,  Yazdan Aghaghiri ,  Massoud Pedram

    IPC分类号： H03M7/00

    CPC分类号： G06F13/4208 ,  Y02D10/14 ,  Y02D10/151

    摘要： A method for reducing transitions on a bus is provided that includes receiving an input trace and constructing a Markov source correlating to the input trace. The method also includes identifying an encoding technique, which can either minimize or maximize an objective function associated with the input trace.

    摘要翻译： 提供了一种用于减少总线上的转换的方法，其包括接收输入轨迹并构建与输入轨迹相关的马尔可夫源。 该方法还包括识别可以最小化或最大化与输入轨迹相关联的目标函数的编码技术。

    Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits
    8.
    发明授权
    Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits 有权
    电荷回收（CR）晶体管在多阈值互补金属氧化物半导体（MTCMOS）电路中的尺寸和放置

    公开(公告)号：US07834684B2

    公开(公告)日：2010-11-16

    申请号：US12263312

    申请日：2008-10-31

    申请人： Farzan Fallah ,  Ehsan Pakbaznia ,  Massoud Pedram

    发明人： Farzan Fallah ,  Ehsan Pakbaznia ,  Massoud Pedram

    IPC分类号： G05F1/10

    CPC分类号： H03K19/0016

    摘要： In one embodiment, a circuit includes a first row of circuit blocks that are each connected to a supply directly and to ground via a first sleep transistor. A connection between the first circuit block and the first sleep transistor is a virtual ground node. The circuit includes a second row of circuit blocks that are each connected to ground directly and to the supply via a second sleep transistor. A connection between the second circuit block and the second sleep transistor is a virtual supply node. The circuit includes a transmission gate (TG) or pass transistor connecting the virtual ground nodes to the virtual supply nodes to enable charge recycling between circuit blocks in the first row and circuit blocks in the second row during transitions by the circuit from active mode to sleep mode, from sleep mode to active mode, or both.

    摘要翻译： 在一个实施例中，电路包括第一行电路块，每个电路块通过第一睡眠晶体管直接连接到电源并接地。 第一电路块和第一休眠晶体管之间的连接是虚拟接地节点。 该电路包括第二排电路块，每个电路块通过第二睡眠晶体管直接连接到接地和电源。 第二电路块和第二睡眠晶体管之间的连接是虚拟供电节点。 该电路包括将虚拟接地节点连接到虚拟供电节点的传输门（TG）或传输晶体管，以便在由电路从活动模式转换到睡眠期间使第一行中的电路块与第二行中的电路块之间的电荷循环 模式，从睡眠模式到活动模式，或两者兼有。

    Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits
    9.
    发明授权
    Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuits 失效
    回收电荷以在多阈值互补金属氧化物半导体（MTCMOS）电路中模式转换期间减少能量消耗

    公开(公告)号：US07400175B2

    公开(公告)日：2008-07-15

    申请号：US11755354

    申请日：2007-05-30

    申请人： Farzan Fallah ,  Ehsan Pakbaznia ,  Massoud Pedram

    发明人： Farzan Fallah ,  Ehsan Pakbaznia ,  Massoud Pedram

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0019 ,  H03K19/0013 ,  H03K19/0016

    摘要： In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a virtual ground node between the first circuit block and the first sleep transistor, a second circuit block connected to a supply via a second sleep transistor, and a virtual supply node between the second circuit block and the second sleep transistor. The circuit also includes a transmission gate (TG) or a pass transistor connecting the virtual ground node to the virtual supply node to enable charge recycling between the first circuit block and the second circuit block during transitions by the circuit between active mode and sleep mode.

    摘要翻译： 在一个实施例中，电路包括经由第一休眠晶体管连接到地的第一电路块，第一电路块和第一休眠晶体管之间的虚拟接地节点，经由第二睡眠晶体管连接到电源的第二电路块，以及 第二电路块和第二睡眠晶体管之间的虚拟供电节点。 该电路还包括传输门（TG）或传输晶体管，其将虚拟接地节点连接到虚拟电源节点，以便在主动模式和休眠模式之间的电路转换期间，使第一电路块和第二电路块之间的电荷再循环。

    Power Mode Transition in Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) Circuits
    10.
    发明申请
    Power Mode Transition in Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) Circuits 有权
    多阈值互补金属氧化物半导体（MTCMOS）电路中的功率模式转换

    公开(公告)号：US20080133954A1

    公开(公告)日：2008-06-05

    申请号：US11421380

    申请日：2006-05-31

    申请人： Farzan Fallah ,  Afshin Abdollahi ,  Massoud Pedram

    发明人： Farzan Fallah ,  Afshin Abdollahi ,  Massoud Pedram

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203

    摘要： In one embodiment, a method for power mode transition in a multi-threshold complementary metal oxide semiconductor (MTCMOS) circuit includes clustering logic cells in the circuit to a number of logic clusters and optimizing wake-up times of the logic clusters to reduce a total turn-on time of the circuit while keeping below a predetermined threshold a sum of currents flowing from the circuit to ground, a sum of currents flowing from a supply voltage to the circuit, or both during a transition by the circuit from sleep mode to active mode.

    摘要翻译： 在一个实施例中，用于多阈值互补金属氧化物半导体（MTCMOS）电路中的功率模式转换的方法包括将电路中的逻辑单元聚集到多个逻辑簇并优化逻辑簇的唤醒时间以减少总计 在电路从休眠模式转换到活动期间，电路的导通时间保持低于预定阈值，从电路流向地的电流的总和，从电源电压流向电路的电流或两者的总和 模式。