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公开(公告)号：US20100142284A1
公开(公告)日：2010-06-10
申请号：US12330928
申请日：2008-12-09
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/04
摘要： Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.
摘要翻译： 提出了使用确定性编程技术来促进存储器中的存储器元件的有效编程的系统，方法和设备。 存储器组件包括优化的程序组件，其可以部分地基于存储器元件的相应电流阈值电压电平（Vt）将被选择用于编程的一组存储器元件划分为期望数量的子组; 将相应的编程脉冲施加到各个子组中的每个存储元件; 在脉冲之后测量存储元件的各个Vt电平; 并且验证为满足目标Vt的传递的存储器元件。优化的程序组件可以部分地基于存储器元件的相应的当前Vt级别将不满足目标Vt的存储器元件的子集划分为期望数量的子组，并且可以 继续执行此确定性编程过程，直到所有存储器元素被验证为传递目标Vt为止。
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公开(公告)号：US07872916B2
公开(公告)日：2011-01-18
申请号：US12330928
申请日：2008-12-09
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/04
摘要： Systems, methods, and devices that employ deterministic programming techniques to facilitate efficient programming of memory elements in a memory are presented. A memory component comprises an optimized program component that can divide a group of memory elements selected for programming into a desired number of subgroups based in part on respective current threshold voltage levels (Vt) of the memory elements; apply respective program pulses to each memory element in respective subgroups; measure respective Vt levels of memory elements after the pulse; and verify as passed memory elements that meet a target Vt. The optimized program component can divide a subset of memory elements that do not meet the target Vt into a desired number of subgroups based in part on respective current Vt levels of the memory elements and can continue to perform this deterministic programming process until all memory elements are verified as passing for the target Vt.
摘要翻译： 提出了使用确定性编程技术来促进存储器中的存储器元件的有效编程的系统，方法和设备。 存储器组件包括优化的程序组件，其可以部分地基于存储器元件的相应电流阈值电压电平（Vt）将被选择用于编程的一组存储器元件划分为期望数量的子组; 将相应的编程脉冲施加到各个子组中的每个存储元件; 在脉冲之后测量存储器元件的各个Vt电平; 并且验证为满足目标Vt的传递的存储器元件。优化的程序组件可以部分地基于存储器元件的相应的当前Vt级别将不满足目标Vt的存储器元件的子集划分为期望数量的子组，并且可以 继续执行此确定性编程过程，直到所有存储器元素被验证为传递目标Vt为止。
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公开(公告)号：US20100135082A1
公开(公告)日：2010-06-03
申请号：US12326388
申请日：2008-12-02
申请人： Fatima Bathul , Darlene Gay Hamilton , Guy Hadas
发明人： Fatima Bathul , Darlene Gay Hamilton , Guy Hadas
CPC分类号： G11C16/04 , G11C16/3454
摘要： Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements to facilitate verifying the cells to pass the first PV level. The PV level can be moved to a next PV level that is a higher charge level than or equal to the first PV level, and a subset of the group of cells that are below the next PV level are selected and a next program pulse is applied to the subset of cells to facilitate verifying the cells to pass the next PV level. The moving PV level process can continue until the group of memory elements is verified to pass the target PV level.
摘要翻译： 提出了采用移动程序验证级别以便于将数据编程到存储器组件中的存储器元件的系统，方法和设备。 程序组件可以采用指定数量的程序验证（PV）级别，其中第一编程脉冲被施加到所选择的存储器单元组，以便于验证单元通过第一PV电平。 PV电平可以移动到比第一PV电平更高的电荷电平的下一个PV电平，并且选择低于下一个PV电平的一组电池的子集，并施加下一个编程脉冲 到细胞的子集以便于验证细胞通过下一个PV水平。 移动光伏电平过程可以继续，直到存储元件组被验证通过目标光伏电平。
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公开(公告)号：US07821840B2
公开(公告)日：2010-10-26
申请号：US12276604
申请日：2008-11-24
申请人： Guy Hadas , Darlene Gay Hamilton , Fatima Bathul
发明人： Guy Hadas , Darlene Gay Hamilton , Fatima Bathul
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages related to specified subgroups associated with respective data levels for a first programming phase. A first programming phase is performed using learned drain voltages as initial drain voltages where drain voltage levels are varied during each program pulse to facilitate programming memory cells to respective intrinsic verify voltage levels based on respective data levels. A second programming phase is performed using ending drain voltages from the first programming phase as initial drain voltages where gate voltage levels are varied during each program pulse to facilitate programming memory cells to respective final verify voltage levels based on respective data levels.
摘要翻译： 介绍了促进存储器组件中数据的多阶段编程的系统，方法和设备。 基于预定义的程序模式，接收的数据被编程到使用多个编程阶段的存储器。 通过根据需要改变漏极电压来执行程序学习，以便于确定与用于第一编程阶段的相应数据电平相关联的与特定子组相关的相应漏极电压。 使用学习的漏极电压作为初始漏极电压来执行第一编程阶段，其中漏极电压电平在每个编程脉冲期间变化，以便于基于相应的数据电平将存储器单元编程到相应的内部验证电压电平。 使用来自第一编程阶段的结束漏极电压作为初始漏极电压来执行第二编程阶段，其中栅极电压电平在每个编程脉冲期间变化，以便于基于相应的数据电平将存储器单元编程到相应的最终验证电压电平。
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公开(公告)号：US20100128524A1
公开(公告)日：2010-05-27
申请号：US12276604
申请日：2008-11-24
申请人： Guy Hadas , Darlene Gay Hamilton , Fatima Bathul
发明人： Guy Hadas , Darlene Gay Hamilton , Fatima Bathul
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Systems, methods, and devices that facilitate multi-phase programming of data in a memory component are presented. Received data is programmed to a memory using multiple programming phases based on a predefined program pattern. A program learn is performed by varying drain voltages, as desired, to facilitate determining respective drain voltages related to specified subgroups associated with respective data levels for a first programming phase. A first programming phase is performed using learned drain voltages as initial drain voltages where drain voltage levels are varied during each program pulse to facilitate programming memory cells to respective intrinsic verify voltage levels based on respective data levels. A second programming phase is performed using ending drain voltages from the first programming phase as initial drain voltages where gate voltage levels are varied during each program pulse to facilitate programming memory cells to respective final verify voltage levels based on respective data levels.
摘要翻译： 介绍了促进存储器组件中数据的多阶段编程的系统，方法和设备。 基于预定义的程序模式，接收的数据被编程到使用多个编程阶段的存储器。 通过根据需要改变漏极电压来执行程序学习，以便于确定与用于第一编程阶段的相应数据电平相关联的与特定子组相关的相应漏极电压。 使用学习的漏极电压作为初始漏极电压来执行第一编程阶段，其中漏极电压电平在每个编程脉冲期间变化，以便于基于相应的数据电平将存储器单元编程到相应的内部验证电压电平。 使用来自第一编程阶段的结束漏极电压作为初始漏极电压来执行第二编程阶段，其中栅极电压电平在每个编程脉冲期间变化，以便于基于相应的数据电平将存储器单元编程到相应的最终验证电压电平。
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公开(公告)号：US08391070B2
公开(公告)日：2013-03-05
申请号：US12326388
申请日：2008-12-02
申请人： Fatima Bathul , Darlene Gay Hamilton , Guy Hadas
发明人： Fatima Bathul , Darlene Gay Hamilton , Guy Hadas
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/3454
摘要： Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements to facilitate verifying the cells to pass the first PV level. The PV level can be moved to a next PV level that is a higher charge level than or equal to the first PV level, and a subset of the group of cells that are below the next PV level are selected and a next program pulse is applied to the subset of cells to facilitate verifying the cells to pass the next PV level. The moving PV level process can continue until the group of memory elements is verified to pass the target PV level.
摘要翻译： 提出了采用移动程序验证级别以便于将数据编程到存储器组件中的存储器元件的系统，方法和设备。 程序组件可以采用指定数量的程序验证（PV）级别，其中第一编程脉冲被施加到所选择的存储器单元组，以便于验证单元通过第一PV电平。 PV电平可以移动到比第一PV电平更高的电荷电平的下一个PV电平，并且选择低于下一个PV电平的一组电池的子集，并施加下一个编程脉冲 到细胞的子集以便于验证细胞通过下一个PV水平。 移动光伏电平过程可以继续，直到存储元件组被验证通过目标光伏电平。
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7.发明申请APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB 有权应用负极门电压到相关的字词相关联的阅读或验证，以减少相似词干扰公开(公告)号：US20100128521A1
公开(公告)日：2010-05-27
申请号：US12275663
申请日：2008-11-21
申请人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
发明人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3427
摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.
摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。
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8.发明授权Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb 有权将负栅极电压施加到与读取或验证相关的字线附近的字线，以减少相邻的字线干扰公开(公告)号：US07995386B2
公开(公告)日：2011-08-09
申请号：US12275663
申请日：2008-11-21
申请人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
发明人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3427
摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.
摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。
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