公开(公告)号：US6128219A

公开(公告)日：2000-10-03

申请号：US428683

申请日：1999-10-27

申请人： Federico Pio ,  Enrico Gomiero ,  Alberto Modelli ,  Paola Paruzzi

发明人： Federico Pio ,  Enrico Gomiero ,  Alberto Modelli ,  Paola Paruzzi

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/0433 ,  G11C16/34

摘要： A test structure is formed by an array of memory cells connected in parallel and including each a memory transistor and a select transistor connected in series. The gate terminals of the select transistors of all memory cells are biased to a value next to the threshold voltage of the select transistors. Therefore, in each memory cell, the drain current is limited by the memory transistor for control gate voltages below the threshold voltage of the memory transistor, and by the select transistor at higher voltages; for high control gate voltages, the drain current is clamped to a constant maximum value. Since the clamping effect of the select transistors acts on each memory cell, the total maximum current of the test structure may be held below a value causing a limitation in the current generated by the entire array because of the resistance in series to the output of the test structure. Thus also the right side of the threshold distribution may be evaluated and the presence of defective cells causing injection of electrons in the floating gate of the memory transistors may be detected.

摘要翻译： 测试结构由并行连接的存储单元的阵列形成，并且包括串联连接的存储晶体管和选择晶体管。 所有存储单元的选择晶体管的栅极端子被偏置成与选择晶体管的阈值电压相邻的值。 因此，在每个存储单元中，漏极电流被存储晶体管限制，用于控制栅极电压低于存储晶体管的阈值电压，并由选择晶体管处于较高电压; 对于高控制栅极电压，漏极电流被钳位到恒定的最大值。 由于选择晶体管的钳位效应作用于每个存储单元，所以测试结构的总最大电流可以被保持在导致由整个阵列产生的电流限制的值，因为与 测试结构。 因此，可以评估阈值分布的右侧，并且可以检测到在存储晶体管的浮动栅极中引起电子注入的缺陷单元的存在。

公开(公告)号：US6144588A

公开(公告)日：2000-11-07

申请号：US150802

申请日：1998-09-10

申请人： Federico Pio ,  Bruno Vajana ,  Paola Paruzzi

发明人： Federico Pio ,  Bruno Vajana ,  Paola Paruzzi

IPC分类号： G11C17/00 ,  G05F3/24 ,  G11C5/14 ,  G11C11/56 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C11/5621 ,  G11C16/30

摘要： A generator for generating a plurality of predetermined voltage values for non-volatile memories. The generator includes an input node, a plurality of circuit branches, and an output terminal. The input node has a reference voltage and is connected to at least one of the circuit branches. Each of the circuit branches has at least one active element to selectively and independently turn on and turn off each of the circuit branches by a voltage applied to a control terminal of each active element. The output terminal connects to at least one of the circuit branches and supplies a voltage level based on the reference voltage and a voltage drop across each activated circuit branch. Alternatively, the output terminal supplies a floating voltage level in the event of one or more of the active elements along each of the circuit branches being turned off so as to isolate the input node from the output terminal.

摘要翻译： 一种用于为非易失性存储器产生多个预定电压值的发生器。 发生器包括输入节点，多个电路分支和输出端子。 输入节点具有参考电压并且连接到至少一个电路分支。 每个电路分支具有至少一个有源元件，以通过施加到每个有源元件的控制端子的电压来选择性地和独立地接通和关断每个电路分支。 输出端子连接到至少一个电路分支，并且基于参考电压提供电压电平，并且在每个激活的电路分支之间提供电压降。 或者，输出端子在沿着每个电路分支的一个或多个有源元件断开的情况下提供浮动电压电平，以将输入节点与输出端子隔离。

公开(公告)号：US5894146A

公开(公告)日：1999-04-13

申请号：US607067

申请日：1996-02-26

申请人： Federico Pio ,  Paola Paruzzi

发明人： Federico Pio ,  Paola Paruzzi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A matrix of EEPROM memory cells having a double polysilicon level of MOS technology and being arranged into rows and columns is monolithically integrated on a substrate of semiconductor material. Each cell comprises, in series, a transistor of the floating gate type which includes two layers of polysilicon superposed on each other and separated by an intervening layer of a dielectric material, and a selection transistor having a gate which comprises a first layer of polysilicon. The gates of the selection transistors in one row of said matrix are connected electrically together by a selection line comprising a second layer of polysilicon overlying the first layer. The intermediate layer of dielectric material is also partly interposed between the first and second layers of polysilicon such that the two layers are in contact at at least one zone of said selection line. Preferably, the contact zone is formed over field oxide regions and is away from the edges of the selection line. The matrix can advantageously be fabricated by a process of the self-aligned type, without making the process any more complicated.

摘要翻译： 具有MOS技术的双重多晶硅级别并被布置成行和列的EEPROM存储单元的矩阵被单片地集成在半导体材料的衬底上。 每个单元串联包括浮置型晶体管，该晶体管包括彼此重叠并由介电材料的中间层隔开的两层多晶硅，以及选择晶体管，其具有包括第一多晶硅层的栅极。 所述矩阵的一行中的选择晶体管的栅极通过包括覆盖在第一层上的第二多晶硅层的选择线电连接。 电介质材料的中间层也部分插入第一和第二多晶硅层之间，使得两层在所述选择线的至少一个区域处接触。 优选地，接触区形成在场氧化物区域上并远离选择线的边缘。 该矩阵可以有利地通过自对准型的工艺制造，而不会使工艺变得更加复杂。

公开(公告)号：US06061269A

公开(公告)日：2000-05-09

申请号：US613443

申请日：1996-03-04

申请人： Livio Baldi ,  Paola Paruzzi

发明人： Livio Baldi ,  Paola Paruzzi

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L29/7885

摘要： The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and lacking the second source diffusion.

摘要翻译： 本发明涉及一种电可编程和可擦除的非易失性存储单元，其具有传统结构，但在组分元件的导电类型中被反转，并且缺少第二源扩散。